Partial access mode for dynamic random access memory

• US 10,020,045 B2
• Filed: 05/22/2014
• Issued: 07/10/2018
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Riho, Yoshiro
• Primary Examiner(s): Tran, Anthan
• Assistant Examiner(s): Siddique, Mushfique
• Application Number:
  US14/285,279
• Publication Number:
  US 20150146494A1
• Time in Patent Office: 1,510 Days
• Field of Search: 365222
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required. One bit data may be stored into 1 cell for a normal operation mode and stored into 2^N cells for a self refresh operation mode for a first partial access mode, while one bit data may be stored into 2^N cells for both normal and self refresh operation modes.

Claims

1. A device comprising:

a plurality of memory cells;

a controller configured to control storage of data in the plurality of memory cells, the controller configured to operate a first access mode which stores one bit data into 1 cell of the memory cells, and a second access mode which stores one bit data into 2^N cells of the memory cells, wherein N is a natural number; and

an address decoder coupled to the controller and configured to simultaneously select one or more word lines coupled to one or more memory cells of the plurality of memory cells to store a data in a self refresh operation mode, the address decoder comprising a logic circuit configured to receive a plurality of code flag signals and a plurality of switches coupled to the logic circuit, and

wherein the controller is configured to operate in the first access mode which activates a word line in a mat to access the one bit data and further configured to operate in the second access mode which simultaneously activates at least one other word line in the mat to access the one bit data, the second access mode being associated with a self refresh operation mode, and

wherein the logic circuit is configured to activate one or more switches of the plurality of switches to select the one or more word lines responsive to the plurality of code flag signals in the second access mode.

2. The device of claim 1, wherein the first access mode is associated with a normal operation mode.

3. The device of claim 1, wherein the controller is configured to operate in the first access mode which activates a word line to access the one bit data and in the second access mode which activates 2^N word lines to access the one bit data.

4. The device of claim 1, wherein the controller is configured in a first partial access mode to operate the first access mode in a normal operation mode and the second access mode in the self refresh operation mode, and further configured in a second partial access mode to operate the second access mode in both the normal operation mode and the self refresh operation mode.

5. The device of claim 4, wherein the controller is configured in a third partial access mode to operate the first access mode in both the normal operation mode and the self refresh operation mode.

6. The device of claim 1, wherein the controller storing causes the power consumption of the device to be a first reduced amount for the first access mode, and causes the power consumption of the device to a second reduced amount for the second access mode, the second reduced amount less than the first reduced amount.

7. A device comprising:

a plurality of memory cells;

a controller controlling storage of data in the plurality of memory cells, the controller configured to store data in the plurality of memory cells as 1 data bit/cell for a normal operation mode and store data in the plurality of memory cells as 1 data bit/2^N cells for a self refresh operation mode in a first partial access mode, and further configured to store data in the plurality of memory cells as 1 data bit/2^N cells for both a normal operation mode and a self refresh operation mode in a second partial access mode, and

an address decoder coupled to the controller and configured to simultaneously select word lines coupled to the plurality of memory cells to store the data in the plurality of memory cells in the self refresh operation mode data, the address decoder comprising a logic circuit and a plurality of switches coupled to the logic circuit,

wherein the logic circuit is configured to receive a plurality of code flag signals and further configured to provide one or more activation signals to one or more switches to select the word lines, and

wherein the plurality of switches is configured to provide a delay in selecting the word lines responsive to the one or more activation signals.

8. The device of claim 7 wherein the address decoder is configured to handle bits of a row address as “

don'"'"'t care”

according to the first or second partial access mode.

9. The device of claim 7, wherein the plurality of memory cells are included in memories of a memory module.