Non main CPU/OS based operational environment

• US 10,078,363 B2
• Filed: 01/15/2016
• Issued: 09/18/2018
• Est. Priority Date: 02/14/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kardach, James P., Belmont, Brian V., Kumar, Muthu K., Jackson, Riley W., Danneels, Gunner D., Forand, Richard A., Gupta, Vivek, Huckins, Jeffrey L., Fleming, Kristoffer D., Gadamsetty, Uma M.
• Primary Examiner(s): Shin, Christopher
• Application Number:
  US14/996,941
• Publication Number:
  US 20160132101A1
• Time in Patent Office: 977 Days
• Field of Search: 713323, 710 15
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G10L 19/04 using predictive techniques
• CPC Class Codes: H04R 1/1091 Details not provided for in groups H04R1/1008 - H04R1/1083
• CPC Class Codes: H04R 2201/109 Arrangements to adapt hands free headphones for use on both ears
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.

Claims

1. An apparatus comprising:

a controller device to be coupled to a plurality of peripheral devices, the controller device comprising;

a microcontroller to facilitate data communication associated with the plurality of peripheral devices when the microcontroller is in an awake state;

a main user-input device to receive inputs for processing by the microcontroller;

a power manager to put the microcontroller into a sleep state and to deactivate the main user-input device to save power;

a non-main user-input device to receive a control input when the main user-input device is deactivated; and

an I/O controller to receive data from a particular peripheral device in the plurality of peripheral devices and to control execution of a function on the data from the particular peripheral device based on the control input from the non-main user-input device without involvement of the microcontroller while the microcontroller is in the sleep state.

2. The apparatus of claim 1, wherein the plurality of peripheral devices comprises a display device.

3. The apparatus of claim 1, wherein the main user-input device comprises a main keyboard and the non-main user-input device comprises a non-main keyboard.

4. The apparatus of claim 1, wherein the apparatus comprises a personal computing device.

5. The apparatus of claim 4, wherein the personal computing device comprises one of a notebook or laptop computer.

6. The apparatus of claim 1, wherein the apparatus facilitates user network communications.

7. The apparatus of claim 1, wherein the I/O controller is to couple to the peripheral devices via a bus.

8. The apparatus of claim 7, further comprising the bus.

9. The apparatus of claim 1, wherein the I/O controller is coupled to at least one of a FLASH memory and a polymer memory.

10. The apparatus of claim 1, wherein at least one of the peripheral devices supports wireless communication.

11. At least one non-transitory machine accessible storage medium having code stored thereon, wherein the code when executed on a machine, causes the machine to:

put a microcontroller of a controller device into a sleep state and deactivate a main user-input device of the controller device to save power, wherein the controller device is coupled to a plurality of peripheral devices, the microcontroller is to facilitate data communication between the plurality of peripheral devices when the microcontroller is in an awake state, and the main user-input device is to receive inputs for processing by the microcontroller;

receive a control input from a non-main user-input device when the main user-input device is deactivated; and

while the microcontroller is in the sleep state and without involvement of the microcontroller;

receive data from one of the plurality of peripheral devices; and

control execution of a function on the data from the one of the plurality of peripheral devices based on the control input from the non-main user-input device.

12. A system comprising:

a plurality of peripheral devices;

a microcontroller to facilitate data communication between at least a portion of the plurality of peripheral devices when the microcontroller is in an awake state;

a main user-input device to receive inputs for processing by the microcontroller;

a power manager to put the microcontroller into a sleep state and to deactivate the main user-input device to save power;

a non-main user-input device to receive a control input when the main user-input device is deactivated; and

an I/O controller to receive data from a particular peripheral device in the plurality of peripheral devices and to control execution of a function on the data from the particular peripheral device based on the control input from the non-main user-input device without involvement of the microcontroller while the microcontroller is in the sleep state.

13. The system of claim 12, wherein the plurality of peripheral devices comprises a display device.

14. The system of claim 12, wherein the main user-input device comprises a main keyboard and the non-main user-input device comprises a non-main keyboard.

15. The system of claim 12, further comprising a personal computing device comprising the microcontroller.

16. The system of claim 15, wherein the personal computing device comprises one of a notebook or laptop computer.

17. The system of claim 15, wherein the personal computing device facilitates network communications.

18. The system of claim 12, further comprising a bus to couple the peripheral devices to the I/O controller.

19. The system of claim 12, further comprising at least one of a FLASH memory and a polymer memory.

20. The system of claim 19, wherein the I/O controller is coupled to at least one of a FLASH memory and a polymer memory.