Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

• US 10,079,314 B2
• Filed: 03/25/2014
• Issued: 09/18/2018
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Levy, Sagy Charel, Jenne, Frederick B., Ramkumar, Krishnaswamy
• Primary Examiner(s): Yushina, Galina
• Application Number:
  US14/225,152
• Publication Number:
  US 20140264550A1
• Time in Patent Office: 1,638 Days
• Field of Search: 257314, 257390, 257E29309, 257E21209, 257E21613, 257E21645, 257E21662, 257E21692
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Claims

1. A nonvolatile charge trap memory device, comprising:

a gate stack disposed above a channel region of a substrate, wherein the gate stack comprises a multi-layer charge-trapping region comprising a first layer and a second layer that is deuterium-free, the first layer disposed between the channel region and the second layer, wherein the first layer comprises a first deuterium concentration, and wherein the multi-layer charge-trapping region further comprises a third layer, the second layer is disposed between the first layer and the third layer, wherein the third layer comprises a second deuterium concentration, and wherein a first abrupt interface is defined by a junction that separates a finite deuterium concentration of the first layer from a zero deuterium concentration of the second layer.

2. The nonvolatile charge trap memory device of claim 1, wherein the second layer is a charge trapping layer.

3. The nonvolatile charge trap memory device of claim 1, further comprising:

a dielectric layer disposed above the multi-layer charge-trapping region.

4. The nonvolatile charge trap memory device of claim 3, wherein the dielectric layer is a high-k dielectric layer comprising at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, or lanthanum oxide.

5. The nonvolatile charge trap memory device of claim 3, wherein the dielectric layer comprises deuterium.

6. The nonvolatile charge trap memory device of claim 3, wherein a thickness of the dielectric layer is in a range of 1-20 nanometers.

7. The nonvolatile charge trap memory device of claim 3, further comprising:

a metallic gate layer disposed above the dielectric layer.

8. The nonvolatile charge trap memory device of claim 1, wherein the gate stack is further disposed between a source region and a drain region.

15. The nonvolatile charge trap memory device of claim 1, further comprising a second abrupt interface that is defined by a junction that separates a finite deuterium concentration of the third layer from the zero deuterium concentration of the second layer.

9. A nonvolatile charge trap memory device, comprising:

a gate stack disposed over a channel region of a substrate, wherein the gate stack comprises;

a tunnel layer on a top surface of the substrate over the channel region; and

a multi-layer charge-trapping region having a first deuterated layer on the tunnel layer and a second deuterium-free charge-trapping layer on the first deuterated layer,

wherein the second deuterium-free charge-trapping layer comprises a trap-dense, oxygen-lean nitride layer and includes a majority of charge traps distributed in the multi-layer charge-trapping region, and wherein a first abrupt interface is defined by a junction that separates a finite deuterium concentration of the first deuterated layer from a zero deuterium concentration of the second deuterium-free charge-trapping layer.

10. The nonvolatile charge trap memory device of claim 9, further comprising:

a dielectric layer disposed above the multi-layer charge-trapping region.

11. The nonvolatile charge trap memory device of claim 10, wherein the dielectric layer is a high-k dielectric layer comprising at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, or lanthanum oxide.

12. The nonvolatile charge trap memory device of claim 10, wherein the dielectric layer comprises deuterium.

13. The nonvolatile charge trap memory device of claim 9, further comprising:

a metallic gate layer disposed above the dielectric layer.

14. The nonvolatile charge trap memory device of claim 9, wherein the gate stack is further disposed between a source region and a drain region.

16. A method comprising:

forming a tunnel dielectric layer on a top surface of a substrate; and

forming a multi-layer charge trapping region on the top surface of the tunnel dielectric layer, wherein the multi-layer charge trapping region comprises a first layer and a second layer, the first layer disposed between the tunnel dielectric layer and the second layer, wherein the first layer comprises a first deuterium concentration, and wherein the multi-layer charge-trapping region further comprises a third layer, wherein the second layer is between the first layer and the third layer and deuterium-free, wherein the third layer comprises a second deuterium concentration, and wherein a first abrupt interface is defined by a junction that separates a finite deuterium concentration of the first layer from a zero deuterium concentration of the second layer.

17. The method of claim 16, further comprising:

forming a high-k dielectric layer disposed on the top surface of the third layer, the high-k dielectric layer comprising at least one of hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride, hafnium zirconium oxide, or lanthanum oxide.

18. The method of 16, wherein a second abrupt interface is defined by a junction that separates a finite deuterium concentration of the third layer from the zero deuterium concentration of the second layer.