Sense amplifier
First Claim
1. A circuit comprising:
- a memory cell; and
a sense amplifier circuit coupled to the memory cell, wherein the sense amplifier circuit includes;
a first path including a first intermediate node;
a second path including a second intermediate node, wherein the sense amplifier circuit is to generate a voltage difference between the first and second intermediate nodes that corresponds to a value of a bit stored by the memory cell;
a latch circuit direct current (DC) coupled between the first and second intermediate nodes, wherein the latch circuit, when activated by an enable signal, is to generate a digital output signal based on the voltage difference between the first and second intermediate nodes;
a cutoff transistor coupled between the first and second paths to turn off responsive to activation of the latch circuit;
a first feedback transistor with a drain terminal coupled to a drain terminal of the cutoff transistor and a gate terminal coupled to the first intermediate node; and
a second feedback transistor with a drain terminal coupled to a source terminal of the cutoff transistor and a gate terminal coupled to the second intermediate node.
3 Assignments
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Accused Products
Abstract
Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.
28 Citations
6 Claims
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1. A circuit comprising:
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a memory cell; and a sense amplifier circuit coupled to the memory cell, wherein the sense amplifier circuit includes; a first path including a first intermediate node; a second path including a second intermediate node, wherein the sense amplifier circuit is to generate a voltage difference between the first and second intermediate nodes that corresponds to a value of a bit stored by the memory cell; a latch circuit direct current (DC) coupled between the first and second intermediate nodes, wherein the latch circuit, when activated by an enable signal, is to generate a digital output signal based on the voltage difference between the first and second intermediate nodes; a cutoff transistor coupled between the first and second paths to turn off responsive to activation of the latch circuit; a first feedback transistor with a drain terminal coupled to a drain terminal of the cutoff transistor and a gate terminal coupled to the first intermediate node; and a second feedback transistor with a drain terminal coupled to a source terminal of the cutoff transistor and a gate terminal coupled to the second intermediate node. - View Dependent Claims (2, 3)
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4. A circuit comprising:
a memory cell; and a sense amplifier circuit coupled to the memory cell, wherein the sense amplifier circuit includes; a first path including a first intermediate node; a second path including a second intermediate node, wherein the sense amplifier circuit is to generate a voltage difference between the first and second intermediate nodes that corresponds to a value of a bit stored by the memory cell; a latch circuit direct current (DC) coupled between the first and second intermediate nodes, wherein the latch circuit, when activated by an enable signal, is to generate a digital output signal based on the voltage difference between the first and second intermediate nodes; a cutoff transistor coupled between the first and second paths to turn off responsive to activation of the latch circuit; first output logic coupled to the first intermediate node to selectively pass a first digital value based on the voltage at the first intermediate node responsive to the enable signal; second output logic coupled to the second intermediate node to selectively pass a second digital value based on the voltage at the second intermediate node responsive to the enable signal, wherein the second digital value is the inverse of the first digital value; and cutoff logic to receive the first and second digital values as inputs and having an output terminal coupled to a gate terminal cutoff transistor to turn off the cutoff transistor responsive to receipt of the first and second digital values. - View Dependent Claims (5, 6)
Specification