Methods and systems for applying an improved interleaver for modems operating on power grid

• US 10,135,467 B2
• Filed: 06/08/2016
• Issued: 11/20/2018
• Est. Priority Date: 06/08/2016
• Status: Active Grant

• Current Assignee: Echelon Corporation (Renesas Electronics Corporation)
• Original Assignee: Echelon Corporation (Renesas Electronics Corporation)
• Inventors: Downey, Walter
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US15/176,979
• Publication Number:
  US 20170359149A1
• Time in Patent Office: 895 Days
• CPC Class Codes: H03M 13/2789 Interleaver providing variable interleaving, e.g. variable block sizes
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

Methods and systems are disclosed for applying an interleaver that better distributes signal errors to be used in devices operating on low voltage power grids. One embodiment of a method comprises: determining a frequency cycle of the communication medium; setting an interleaver block size based on the frequency cycle of the communication medium; re-arranging bits in a data packet based on the interleaver block size; transmitting the re-arranged data packet over the communication medium to a receiver. Specifically, according to an embodiment, the interleaver block size is set to one-half of the frequency cycle of the communication medium.

Claims

1. A method for transmitting data over a communication medium using interleaver error distribution, the communication medium being a low voltage power grid, the method comprising:

determining, by frequency detector circuitry, a frequency cycle of the communication medium;

setting, by interleaver processor circuitry, an interleaver block size to one-half of the determined frequency cycle of the communication medium;

rearranging, by encoder circuitry, bits in a data packet based on the interleaver block size; and

transmitting, by input/output (I/O) circuitry, the re-arranged data packet over the communication medium to a receiver.

2. The method of claim 1, wherein the communication medium uses an alternating current (AC) waveform as a frequency of 50 Hz.

3. The method of claim 1, wherein the communication medium uses an alternating current (AC) waveform as a frequency of 60 Hz.

4. An apparatus comprising:

frequency detector circuitry to detect a frequency cycle of a communication medium to which the apparatus is coupled to, the communication medium being a low voltage power grid;

interleaver processor circuitry to set an interleaver block size to one-half of the detected frequency cycle of the communication medium;

encoder circuitry to re-arrange bits in a data packet based on the interleaver block size; and

input/output (I/O) circuitry to transmit the re-arranged data packet over the communication medium.

5. The apparatus of claim 4, wherein the communication medium uses an alternating current (AC) waveform as a frequency of 50 Hz.

6. The apparatus of claim 4, wherein the communication medium uses an alternating current (AC) waveform as a frequency of 60 Hz.