FETs and methods for forming the same

• US 10,164,116 B2
• Filed: 10/24/2017
• Issued: 12/25/2018
• Est. Priority Date: 02/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Lien, Fan, Chun-Hsiang, Lee, Tung Ying, Liu, Chi-Wen
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US15/791,660
• Publication Number:
  US 20180061988A1
• Time in Patent Office: 427 Days
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/122 Single quantum well structures single heterojunctions, couples of materials H01L29/165, H01L29/205, H01L29/225, H01L29/267
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66977 Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first epitaxial structure over a substrate in an NMOS region;

forming a second epitaxial structure over the substrate in a PMOS region;

forming a shallow trench isolation (STI) region between the first epitaxial structure and the second epitaxial structure;

patterning the first epitaxial structure and the second epitaxial structure to form a first plurality of vertical channel structures and a second plurality of vertical channel structures, respectively;

reshaping the first plurality of vertical channel structures and the second plurality of vertical channel structures, wherein after the reshaping, sidewalls of the first plurality of vertical channel structures and sidewalls the second plurality of vertical channel structures have lattice shifts;

forming a gate dielectric layer in first openings between the first plurality of vertical channel structures and in second openings between the second plurality of vertical channel structures;

filling the first openings and the second openings with a conductive material; and

growing a first epitaxial source/drain material over the first plurality of vertical channel structures and a second epitaxial source/drain material over the second plurality of vertical channel structures.

2. The method of claim 1, wherein forming the first epitaxial structure comprises:

forming a first epitaxial material in the NMOS region and over the substrate;

forming a second epitaxial material over the first epitaxial material in the NMOS region, the second epitaxial material being different from the first epitaxial material; and

forming a third epitaxial material over the second epitaxial material in the NMOS region, the third epitaxial material being different from the second epitaxial material.

3. The method of claim 2, wherein the first epitaxial material is the same as the third epitaxial material.

4. The method of claim 1, further comprising:

forming a P-well region between the first epitaxial structure and the substrate the; and

forming an N-well region between the second epitaxial structure and the substrate.

5. The method of claim 1, wherein the reshaping comprises performing a wet etch process.

6. The method of claim 5, wherein the wet etch process is performed using an etching species comprising hydrochloric acid and ammonium hydroxide.

7. The method of claim 1, wherein the reshaping comprises a dry etch process.

8. The method of claim 7, wherein the dry etch process is performed using reaction gases comprising a fluorine-based gas, chloride, hydrogen bromide, oxygen, the like, or combinations thereof.

9. The method of claim 1, wherein the reshaping comprises an anneal process.

10. The method of claim 9, wherein the anneal process is performed at a temperature between about 500°

C. and about 800°

C.

11. The method of claim 1, wherein after the reshaping, a crystalline structure along sidewalls of a first vertical channel structure of the first plurality of vertical channel structures has lattice shifts, wherein the lattice shifts shift inward toward a center of the first vertical channel structure or outward away from the center of the first vertical channel structure.

12. The method of claim 11, wherein a distance between two adjacent lattice shifts is in a range between about 2 atoms and about 20 atoms.

13. A method of forming a semiconductor device, the method comprising:

forming an epitaxial structure over a substrate, wherein forming the epitaxial structure comprises forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer successively over the substrate;

patterning the epitaxial structure to form openings in the epitaxial structure, wherein the openings extend through the third epitaxial layer, through the second epitaxial layer, and into the first epitaxial layer, wherein after the patterning, remaining portions of the third epitaxial layer and remaining portions of the second epitaxial layer form a plurality of vertical channel structures, and remaining portions of the first epitaxial layer form a first source/drain region;

reshaping the plurality of vertical channel structures, wherein after the reshaping, sidewalls of each of the plurality of the vertical channel structures comprise at least one lattice shift inward or outward relative to a center of a respective vertical channel structure;

forming a metal gate in the openings; and

forming an epitaxial material over the plurality of vertical channel structures to form a second source/drain region.

14. The method of claim 13, wherein forming the metal gate comprises:

lining the openings with a gate dielectric layer; and

filling the openings with a conductive material after the lining to form a gate electrode.

15. The method of claim 13, wherein the metal gate encircles the plurality of vertical channel structures.

16. The method of claim 13, wherein after the reshaping, a sidewall of a vertical channel structure form a deviation angle with a normal of a major surface of the substrate, the deviation angle exceeding 2°

.

17. A method of forming a semiconductor device, the method comprising:

forming a first epitaxial source/drain layer, an epitaxial channel layer, and a second epitaxial source/drain layer successively over a substrate;

forming a patterned mask layer over the second epitaxial source/drain layer;

performing an etching process using the patterned mask layer to remove portions of the first epitaxial source/drain layer, portions of the epitaxial channel layer, and portions of the second epitaxial source/drain layer, wherein remaining portions of the second epitaxial source/drain layer and remaining portions of the epitaxial channel layer form a vertical channel structure that protrudes over remaining portions of the first epitaxial source/drain layer;

reshaping the vertical channel structure, wherein after the reshaping, sidewalls of the vertical channel structure have lattice shifts;

forming a gate dielectric layer and a gate electrode around the vertical channel structure;

recessing a top surface of the gate dielectric layer and a top surface of the gate electrode below a top surface of the remaining portions of the epitaxial channel layer;

forming a first dielectric layer over the recessed gate dielectric layer and over the recessed gate electrode; and

growing an epitaxial material on a top surface of the remaining portions of the second epitaxial source/drain layer.

18. The method of claim 17, further comprising forming a second dielectric layer over the remaining portions of the first epitaxial source/drain layer before reshaping the vertical channel structure.

19. The method of claim 18, wherein forming a gate dielectric layer and a gate electrode comprises:

conformally forming the gate dielectric layer over sidewalls of the vertical gate structure and over an upper surface the second dielectric layer; and

forming a metal-containing material over the gate dielectric layer to form the gate electrode.

20. The method of claim 17, wherein reshaping the vertical channel structure comprises performing a dry etching process, a wet etch process, or an anneal process, wherein the reshaping shifts the sidewalls of the vertical channel structure inward toward a center of the vertical channel structure or outward away from the center of the vertical channel structure.