Circuit and architecture for a demodulator for a wireless power transfer system and method therefor

• US 10,181,754 B2
• Filed: 06/06/2016
• Issued: 01/15/2019
• Est. Priority Date: 12/16/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Khandelwal, Ashish, Khayat, Joseph M., Su, Yipeng, Neidorff, Robert A., Kannan, Bharath B.
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/174,601
• Publication Number:
  US 20160352146A1
• Time in Patent Office: 953 Days
• Field of Search: 307104
• CPC Class Codes: H02J 50/10 using inductive coupling
• CPC Class Codes: H02J 50/80 involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• CPC Class Codes: H02J 7/00034 Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 2005/00078 Fixed delay
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02
• CPC Class Codes: H03K 5/1536 Zero-crossing detectors in measuring circuits G01R19/175
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H04B 5/266 One coil at each side, e.g. with primary and secondary coils
• CPC Class Codes: H04B 5/48 Transceivers
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer

Abstract

A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

Claims

1. A demodulator circuit for use in a wireless power transfer system, the demodulator circuit comprising:

a buffer having a non-inverting input, an inverting input, and an output, the non-inverting input configured to be coupled to a tank circuit, the inverting input coupled to the output;

a sample and hold (SH) circuit including a switch having a first terminal coupled to the output of the buffer, and a capacitor coupled between a second terminal of the switch and a ground terminal;

a phase delay generator circuit having an input coupled to the output of the buffer, and an output coupled to a control terminal of the switch of the SH circuit; and

a comparator coupled to the second terminal of the switch of the SH.

2. The demodulator circuit of claim 1, further comprising:

a reference voltage source;

a first resistor coupled between the reference voltage source and the non-inverting input of the buffer; and

a second resistor coupled between the non-inverting input of the buffer and a ground terminal.

3. The demodulator circuit of claim 1, further comprising:

an input terminal configured to be coupled to the tank circuit;

a first resistor coupled between the input terminal and a node;

a second resistor coupled between the node and a ground terminal; and

an input capacitor coupled between the node and the non-inverting input of the buffer.

4. The demodulator circuit of claim 1, further comprising:

a differentiator circuit coupled to the output of the buffer circuit; and

a slope detector circuit coupled between the differentiator circuit and the phase delay generator circuit,

wherein the input of the phase delay generator circuit coupled to the output of the buffer via the differentiator circuit and the slope detector circuit.

5. The demodulator circuit of claim 1, wherein the phase delay generator circuit is configured to generate a pulse signal having a 45 degrees phase delay from the output of the buffer.

6. The demodulator circuit of claim 1, further comprising:

a low pass filter coupled between the second terminal of the switch and the comparator.

7. The demodulator circuit of claim 6, further comprising:

an RC filter coupled between the low pass filter and the comparator,

wherein the comparator has a non-inverting input coupled to the low pass filter via the RC filter, and an inverting input coupled to the low pass filter and bypassing the RF filter.

8. The demodulator circuit of claim 6, further comprising:

a threshold detection circuit coupled between the low pass filter and the comparator,

wherein the comparator has a non-inverting input coupled to the low pass filter via the threshold detection circuit, and an inverting input coupled to the low pass filter and bypassing the threshold detection circuit.

9. The demodulator circuit of claim 8, wherein the threshold detection circuit includes a peak detector and a valley detector parallel to the peak detector.

10. The demodulator circuit of claim 1, wherein the buffer is configured to receive a DC bias near zero volt.

11. The demodulator circuit of claim 1, wherein the buffer is configured to receive a DC bias at 200 mV.

12. The demodulator circuit of claim 1, wherein the buffer includes an open loop buffer circuit.