RF switch having reduced signal distortion
First Claim
1. An RF switch having a common mode (CM) node, a first end node, and a second end node comprising:
- an M number of FETs that are stacked in series and coupled between the first end node and the second end node wherein M is a finite number greater than one and each of the M number of FETs has a gate;
a resistive network coupled between the CM node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal; and
biasing circuitry coupled to the CM node and configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.
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Accused Products
Abstract
An RF switch having an M number of FETs that are stacked in series and coupled between a first end node and a second end node wherein each of the M number of FETs has a gate is disclosed. A resistive network is coupled between a common mode (CM) node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal. Biasing circuitry coupled to the CM node is configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.
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Citations
21 Claims
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1. An RF switch having a common mode (CM) node, a first end node, and a second end node comprising:
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an M number of FETs that are stacked in series and coupled between the first end node and the second end node wherein M is a finite number greater than one and each of the M number of FETs has a gate; a resistive network coupled between the CM node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal; and biasing circuitry coupled to the CM node and configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification