Fan-out structure and method of fabricating the same

• US 10,297,471 B2
• Filed: 08/16/2017
• Issued: 05/21/2019
• Est. Priority Date: 12/15/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Su, An-Jhih, Wu, Chi-Hsi, Yeh, Der-Chyang, Chen, Hsien-Wei, Chen, Wei-Yu
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US15/678,788
• Publication Number:
  US 20180174865A1
• Time in Patent Office: 643 Days
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/28 : Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor structure and a method of forming include a first semiconductor die and a first dummy die over a carrier, wherein a thickness of the first semiconductor die is greater than a thickness of the first dummy die, a first molding compound layer over the carrier, the first molding compound layer extending along sidewalls of the first semiconductor die and the first dummy die and a first interconnect structure over the first molding compound layer, wherein the first interconnect structure comprises a first metal feature electrically coupled to the first semiconductor die and the first molding compound layer is formed between the first dummy die and the first metal feature.

Claims

1. A method comprising:

attaching a first semiconductor die and a first dummy die to a carrier, wherein a thickness of the first semiconductor die is greater than a thickness of the first dummy die, and wherein a first sidewall of the first dummy die is adjacent to the first semiconductor die, and a second sidewall of the first dummy die is parallel with the first sidewall and the second sidewall is a farthest sidewall with respect to the first semiconductor die;

forming a first molding compound layer over the carrier, the first molding compound layer extending along sidewalls of the first semiconductor die and the first dummy die; and

forming a first interconnect structure over the first molding compound layer, wherein;

the first interconnect structure comprises a first metal feature electrically coupled to the first semiconductor die;

the first interconnect structure comprises a second metal feature directly over the first dummy die, and wherein the second metal feature extends over and laterally overlaps the second sidewall of the first dummy die; and

the first molding compound layer is formed between the first dummy die and the first metal feature and wherein the second metal feature of the first interconnect structure and the first dummy die are separated only by dielectric materials.

2. The method of claim 1, wherein:

forming the first molding compound layer over the carrier comprises performing a thinning process on the first molding compound layer until a top surface of the first semiconductor die is exposed.

3. The method of claim 1, further comprising:

attaching a second dummy die to the carrier, wherein;

the thickness of the first semiconductor die is greater than a thickness of the second dummy die; and

the second dummy die and the first dummy die are on opposite sides of the first semiconductor die.

4. The method of claim 1, further comprising:

attaching a second dummy die, a third dummy die and a fourth dummy die to the carrier, wherein;

the thickness of the first semiconductor die is greater than thicknesses of the second dummy die, the third dummy die and the fourth dummy die;

the first dummy die and the second dummy die are on opposite sides of the first semiconductor die with reference to a first direction; and

the third dummy die and the fourth dummy die are on opposite sides of the first semiconductor die with reference to a second direction, wherein the first direction is orthogonal to the second direction.

5. The method of claim 4, wherein:

a length of the first semiconductor die is substantially equal to a length of the first dummy die.

6. The method of claim 1, further comprising:

mounting a second semiconductor die and a second dummy die over the first interconnect structure, wherein a thickness of the second semiconductor die is greater than a thickness of the second dummy die;

forming a second molding compound layer over the first interconnect structure, the second molding compound layer extending along sidewalls of the second semiconductor die and the second dummy die; and

forming a second interconnect structure over the second molding compound layer, wherein the second molding compound layer electrically insulates a second metal feature of the second interconnect structure from the second dummy die.

7. The method of claim 6, wherein:

a center of the second dummy die is vertically aligned with a center of the first dummy die.

8. The method of claim 6, wherein:

a center of the second dummy die is vertically aligned with a center of the first semiconductor die.

9. The method of claim 1, further comprising:

forming a first via and a second via in the first molding compound layer, wherein the first semiconductor die and the first dummy die are between the first via and the second via; and

mounting a top package over the first molding compound layer, wherein a first bump of the top package and the first via form a joint structure.

10. The method of claim 1, wherein:

the first semiconductor die comprises a plurality of active circuits; and

the first dummy die is free of any active circuits.

11. A method comprising:

attaching a first side of a first semiconductor die and a first side of a first dummy die to a carrier, wherein a first sidewall of the first dummy die is adjacent to the first semiconductor die, and a second sidewall of the first dummy die is parallel with the first sidewall and the second sidewall is a farthest sidewall with respect to the first semiconductor die, and wherein;

a thickness of the first semiconductor die is greater than a thickness of the first dummy die;

forming a first molding compound layer over the carrier, wherein a second side of the first semiconductor die and a second side the first dummy die are covered by the first molding compound layer;

performing a thinning process on the first molding compound layer until a surface of the second side of the first semiconductor die is exposed, wherein the first dummy die remains covered by the first molding compound layer after the thinning process;

depositing a dielectric layer over and in contact with the first molding compound layer; and

after the step of depositing a dielectric layer, forming a first interconnect structure over and in contact with the dielectric layer, wherein a metal feature of the first interconnect structure extends over and laterally overlaps the second sidewall of the first dummy die, and the second side of the first dummy die and the metal feature of the first interconnect structure are separated by the first molding compound layer.

15. The method of claim 11, further comprising detaching the carrier from the first semiconductor die and the first dummy die, wherein after the step of detaching the carrier, a surface of the first side of the first semiconductor die is substantially level with a surface of the first side of the first dummy die.

12. The method of claim ii, further comprising:

mounting a second semiconductor die and a second dummy die over the first interconnect structure, wherein a thickness of the second semiconductor die is greater than a thickness of the second dummy die;

forming a second molding compound layer over the first interconnect structure, the second molding compound layer extending along sidewalls of the second semiconductor die and the second dummy die; and

forming a second interconnect structure over the second molding compound layer, wherein the second dummy die and the second interconnect structure are separated by the second molding compound layer.

13. The method of claim 12, wherein a center of the second dummy die is vertically aligned with a center of the first semiconductor die.

14. The method of claim 12, wherein an edge of the second dummy die is vertically aligned with an edge of the first semiconductor die.

16. An apparatus comprising:

a first semiconductor die and a first dummy die in a first molding compound layer, wherein a first sidewall of the first dummy die is adjacent to the first semiconductor die, and a second sidewall of the first dummy die is parallel with the first sidewall and the second sidewall is a farthest sidewall with respect to the first semiconductor die, and wherein;

a thickness of the first semiconductor die is greater than a thickness of the first dummy die; and

a first side of the first semiconductor die is substantially level with a first side of the first dummy die;

a first interconnect structure over the first molding compound layer, wherein;

the first interconnect structure comprises a first metal feature over the first semiconductor die and a second metal feature directly over the first dummy die, and the second metal feature laterally overlaps the second sidewall of the first dummy die;

a second side of the first semiconductor die is in contact with the first metal feature of the first interconnect structure; and

a second side of the first dummy die and the second metal feature of the first interconnect structure are separated only by dielectric materials; and

a plurality of bumps over the first interconnect structure.

17. The apparatus of claim 16, further comprising:

a second dummy die in the first molding compound layer, wherein;

the first dummy die and the second dummy die are on opposite sides of the first semiconductor die;

the thickness of the first semiconductor die is greater than a thickness of the second dummy die; and

the first dummy die and the second dummy die are free of any active circuits.

18. The apparatus of claim 16, further comprising:

a second dummy die, a third dummy die and a fourth dummy die in the first molding compound layer, wherein;

the thickness of the first semiconductor die is greater than thicknesses of the second dummy die, the third dummy die and the fourth dummy die;

the first dummy die is placed along a first sidewall of the first semiconductor die;

the second dummy die is placed along a second sidewall of the first semiconductor die;

the third dummy die is placed along a third sidewall of the first semiconductor die; and

the fourth dummy die is placed along a fourth sidewall of the first semiconductor die.

19. The apparatus of claim 16, further comprising:

a second interconnect structure extending along a surface of the first molding compound layer;

a second molding compound layer extending along a surface of the second interconnect structure; and

a second semiconductor die and a second-level dummy die in the second molding compound layer.

20. The apparatus of claim 19, wherein:

a center of the second-level dummy die is vertically aligned with a center of the first semiconductor die.