Semiconductor memory device and method with temperature detection
First Claim
1. A method of operating a semiconductor memory device including a plurality of memory cells, the method comprising:
- receiving a request for performing a target operation from a controller configured to control the semiconductor memory device;
generating a synchronizing signal for performing the target operation, wherein the synchronizing signal includes an operation start pulse and an operation end pulse; and
detecting temperatures of memory cells included in the semiconductor memory device in response to a chip selection signal or the operation end pulse,wherein the operation start pulse represents that the target operation starts is generated,wherein the operation end pulse represents that the target operation ends is generated, andwherein the chip selection signal is enabled when the semiconductor memory device to be used is selected.
1 Assignment
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Accused Products
Abstract
There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.
3 Citations
19 Claims
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1. A method of operating a semiconductor memory device including a plurality of memory cells, the method comprising:
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receiving a request for performing a target operation from a controller configured to control the semiconductor memory device; generating a synchronizing signal for performing the target operation, wherein the synchronizing signal includes an operation start pulse and an operation end pulse; and detecting temperatures of memory cells included in the semiconductor memory device in response to a chip selection signal or the operation end pulse, wherein the operation start pulse represents that the target operation starts is generated, wherein the operation end pulse represents that the target operation ends is generated, and wherein the chip selection signal is enabled when the semiconductor memory device to be used is selected. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor memory device comprising:
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a memory cell array including a plurality of memory cells; an operation control signal generator configured to receive a request for performing a target operation from a controller and to generate a synchronizing signal, wherein the synchronizing signal includes an operation start pulse and an operation end pulse, for performing the target operation; and a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to a chip selection signal or the operation end pulse, wherein the operation start pulse representing that the target operation starts is generated, wherein the operation end pulse representing that the target operation ends is generated, and wherein the chip selection signal is enabled when the semiconductor memory device to be used is selected. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification