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Multilayer pillar for reduced stress interconnect and method of making same

  • US 10,396,051 B2
  • Filed: 01/13/2017
  • Issued: 08/27/2019
  • Est. Priority Date: 10/11/2007
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • providing a chip having a barrier and adhesion layer;

    forming a seed layer on the barrier and adhesion layer;

    forming a first copper layer on the seed layer;

    forming a first intermediate layer on the first copper layer;

    forming a second copper layer on first intermediate layer;

    forming a second intermediate layer in direct contact with the second copper layer;

    forming a third copper layer in direct contact with the second intermediate layer; and

    forming a first barrier protective layer at an interface between the first copper layer and the first intermediate layer,wherein the barrier and adhesion layer is Titanium Tungsten and the first barrier protective layer is nickel.

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