Methods for phase-change memory array
First Claim
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1. A method of operating a memory structure, comprising:
- determining a pattern to be written to the memory structure, the memory structure comprising multiple memory cells having a storage element including a chalcogenide material, the pattern comprising both real data bits representing data to be stored and fake data bits having a state that is unimportant to the data to be stored;
writing the pattern to a group of the memory cells; and
prior to writing the data bits and fake data bits to the group of memory cells, receiving a password associated with a memory operation, comparing the password to a password stored in the memory structure,determining a match between the received write password and the stored password, andin response to determining the match, performing at least two reset operations on at least the group of memory cells, wherein each reset operation comprises providing at least one of, one or more hard reset pulses or one or more soft reset pulses, to the group of memory cells.
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Abstract
Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.
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Citations
18 Claims
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1. A method of operating a memory structure, comprising:
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determining a pattern to be written to the memory structure, the memory structure comprising multiple memory cells having a storage element including a chalcogenide material, the pattern comprising both real data bits representing data to be stored and fake data bits having a state that is unimportant to the data to be stored; writing the pattern to a group of the memory cells; and prior to writing the data bits and fake data bits to the group of memory cells, receiving a password associated with a memory operation, comparing the password to a password stored in the memory structure, determining a match between the received write password and the stored password, and in response to determining the match, performing at least two reset operations on at least the group of memory cells, wherein each reset operation comprises providing at least one of, one or more hard reset pulses or one or more soft reset pulses, to the group of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of operating a memory structure, comprising:
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determining a pattern to be written to the memory structure, the memory structure comprising multiple memory cells having a storage element including a chalcogenide material, the pattern comprising both real data bits representing data to be stored and fake data bits having a state that is unimportant to the data to be stored; writing the pattern to a group of the memory cells; receiving a password associated with a memory operation; comparing the password to a password stored in the memory structure; determining a non-match between the received password and the stored password; and in response to determining the non-match, performing an erase operation on at least the group of memory cells. - View Dependent Claims (13)
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14. A system, comprising:
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a memory array including multiple memory cells including storage elements comprising a chalcogenide material; a memory block separate from the memory array, the memory block configured to include system information including passwords for memory operations on the memory array; one or more processors coupled to the memory array configured to, determine a pattern to be written to a group of memory cells of the memory array, the pattern comprising both real data bits having a state representative of data to be stored, and fake data bits having a state that is unimportant to the data of the real data bits, compare a received password associated with a requested memory operation to a password stored in the memory block to determine whether the received password matches the stored password; and in response the determination, performing one of multiple possible operations on at least the group of memory cells; and an internal state machine coupled to the memory array and configured to write the pattern to the group of memory cells of memory array. - View Dependent Claims (15, 16, 17, 18)
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Specification