Circuit and method for storing information in non-volatile memory during a loss of power event

• US 10,430,296 B2
• Filed: 09/29/2017
• Issued: 10/01/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Cesaretti, Juan Manuel, Milesi, Alejandro Gabriel
• Primary Examiner(s): King, Douglas
• Application Number:
  US15/720,533
• Publication Number:
  US 20190102261A1
• Time in Patent Office: 732 Days
• Field of Search: None
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

Claims

1. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising:

a non-volatile matrix of memory cells comprising a plurality of rows and a plurality of columns of memory cells including an independent row of memory cells and a controller comprising a plurality of drivers including row and column drivers and an independent driver, the controller configured to;

in the absence of a power loss, write data from the volatile memory to the non-volatile matrix of memory cells by utilizing the row and column drivers to perform collective row and column operations; and

in response to receiving a power loss signal write data from said volatile memory to said independent row of memory cells by selectively supplying energy to the independent row driver and not the row and column drivers.

2. The data storage circuit of claim 1 further comprising an energy storage device:

wherein the non-volatile matrix of memory cells forms the memory of an EEPROM, wherein the row and column drivers are EEPROM row and column drivers arranged and configured to coordinate reading and writing to multiple rows and columns of the EEPROM; and

wherein the controller is configured, in response to the power loss signal, to selectively direct energy from the energy storing device to said independent driver for writing of data from said volatile memory.

3. The data storage circuit of claim 2 further comprising a clock signal generator, wherein the coordinated reading and writing from said plurality of column and row drivers is timed to a dock signal from the dock signal generator and wherein the writing of data from said volatile memory to said independent row of memory cells in response to the power loss signal is controlled without utilizing a clock signal.

4. The data storage circuit of claim 3 wherein the controller is configured to write to the independent row of memory cells in response to a power loss signal without overwriting at least a portion of the plurality of memory cells of the EEPROM.

5. The data storage circuit of claim 4 wherein the controller is configured to write to the independent row of memory cells in response to a power loss signal without writing to any other of the plurality of memory cells of the EEPROM.

6. The data storage circuit of claim 5 further comprising an independent memory driver configured to be selectively powered from the energy storing device to write to the independent row memory cells in response to a power loss signal.

7. The data storage circuit of claim 6 wherein the energy storing device comprises a charge pump and a charge pump switch configured to release power stored in the charge pump when switched, the charge pump switch coupled between the charge pump and the independent memory driver and configured to switch closed by receiving a signal from the controller in response to the power loss signal.

8. The data storage circuit of claim 2 wherein the controller is arranged and configured to write data from said volatile memory to said independent row of memory cells in less than about 10 milliseconds.

9. A method of transferring data from a volatile memory circuit to an EEPROM during a power interruption, the method comprising:

transmitting a power loss signal in a primary circuit, the power loss signal representing that a power supply coupled to the primary circuit has been interrupted; and

receiving the power loss signal in a controller, the controller comprising row and column drivers and an independent driver and configured to, in response to receiving the power loss signal, write data from the volatile memory circuit to an independent EEPROM memory row of a matrix of memory cells of the EEPROM using the independent driver, the matrix having a plurality of rows and a plurality of columns of memory cells, wherein the writing occurs while only powering the independent driver and not powering any of the row and column drivers; and

operating the matrix of memory cells, including the independent memory row with the row and column drivers, utilizing collective row and column EEPROM operations while the power loss signal is not active.

10. The method of claim 9 wherein the writing to the independent row of the EEPROM is powered by residual power in the primary circuit.

11. The method of claim 10 wherein the residual power is supplied by power stored in a charge pump, the charge pump'"'"'s residual power released by switching a charge pump switch in response to the power loss signal.

12. The method of claim 9 wherein writing data from the volatile memory circuit to an independent EPROM row is executed without utilizing a clock signal.