Circuit and method for storing information in non-volatile memory during a loss of power event
First Claim
1. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising:
- a non-volatile matrix of memory cells comprising a plurality of rows and a plurality of columns of memory cells including an independent row of memory cells and a controller comprising a plurality of drivers including row and column drivers and an independent driver, the controller configured to;
in the absence of a power loss, write data from the volatile memory to the non-volatile matrix of memory cells by utilizing the row and column drivers to perform collective row and column operations; and
in response to receiving a power loss signal write data from said volatile memory to said independent row of memory cells by selectively supplying energy to the independent row driver and not the row and column drivers.
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Accused Products
Abstract
A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).
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Citations
12 Claims
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1. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising:
- a non-volatile matrix of memory cells comprising a plurality of rows and a plurality of columns of memory cells including an independent row of memory cells and a controller comprising a plurality of drivers including row and column drivers and an independent driver, the controller configured to;
in the absence of a power loss, write data from the volatile memory to the non-volatile matrix of memory cells by utilizing the row and column drivers to perform collective row and column operations; and
in response to receiving a power loss signal write data from said volatile memory to said independent row of memory cells by selectively supplying energy to the independent row driver and not the row and column drivers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- a non-volatile matrix of memory cells comprising a plurality of rows and a plurality of columns of memory cells including an independent row of memory cells and a controller comprising a plurality of drivers including row and column drivers and an independent driver, the controller configured to;
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9. A method of transferring data from a volatile memory circuit to an EEPROM during a power interruption, the method comprising:
- transmitting a power loss signal in a primary circuit, the power loss signal representing that a power supply coupled to the primary circuit has been interrupted; and
receiving the power loss signal in a controller, the controller comprising row and column drivers and an independent driver and configured to, in response to receiving the power loss signal, write data from the volatile memory circuit to an independent EEPROM memory row of a matrix of memory cells of the EEPROM using the independent driver, the matrix having a plurality of rows and a plurality of columns of memory cells, wherein the writing occurs while only powering the independent driver and not powering any of the row and column drivers; and
operating the matrix of memory cells, including the independent memory row with the row and column drivers, utilizing collective row and column EEPROM operations while the power loss signal is not active. - View Dependent Claims (10, 11, 12)
- transmitting a power loss signal in a primary circuit, the power loss signal representing that a power supply coupled to the primary circuit has been interrupted; and
Specification