System on chip including clock management unit and method of operating the system on chip

• US 10,430,372 B2
• Filed: 05/17/2016
• Issued: 10/01/2019
• Est. Priority Date: 05/26/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Ho-yeon, Lee, Jae-gon, Choi, Youn-sik, Lee, Min-joung, Song, Jin-ook
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US15/156,825
• Publication Number:
  US 20160350259A1
• Time in Patent Office: 1,232 Days
• Field of Search: None
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Claims

1. Clock management circuitry, comprising:

a first master clock controller configured to provide a first command to a first slave clock controller via a first channel and a second command to a second slave clock controller via a second channel, based on a first clock request;

the first slave clock controller configured to control an output of a first clock signal based on the first command; and

the second slave clock controller configured to control an output of a second clock signal based on the second command,

wherein the first master clock controller is further configured to provide the second command to the second slave clock controller via the second channel after receiving a first acknowledgement from the first slave clock controller, and

the first master clock controller is configured to perform a clock gating operation after receiving the first acknowledgement indicating that the first slave clock controller has completed a controlling operation with respect to the output of the first clock signal, and a second acknowledgement indicating that the second slave clock controller has completed a controlling operation with respect to the output of the second clock signal.

2. The clock management circuitry of claim 1, wherein the first master clock controller is configured to receive the first clock request from a processor.

3. The clock management circuitry of claim 1, wherein the first master clock controller is configured to receive the first clock request via a third channel from a hardware component.

4. The clock management circuitry of claim 1, wherein

the first slave clock controller is configured to send the first acknowledgement to the first master clock controller via the first channel in response to the output of the first clock signal;

and

the first master clock controller is configured to output a third clock signal after receipt of the first acknowledgement.

5. The clock management circuitry of claim 1, wherein the first slave clock controller is configured to receive a second clock request from a hardware component and is configured to control generation of the first clock signal based on the first command and the second clock request.

6. The clock management circuitry of claim 5, wherein the first slave clock controller is further configured to control the generation of the first clock signal based on an earlier received one of the first command and the second clock request.

7. The clock management circuitry of claim 5, wherein the first slave clock controller is further configured to control the generation of the first clock signal based on a selected one of the first command and the second clock request.

8. The clock management circuitry of claim 5, wherein the first slave clock controller is further configured to control the generation of the first clock signal based on additional information included in at least one of the first command and the second clock request.

9. The clock management circuitry of claim 1, wherein the first slave clock controller is configured to receive the first clock request, and the first slave clock controller is further configured to control generation of the first clock signal in response to at least one of the first clock request and the first command.

10. The clock management circuitry of claim 1, wherein the first master clock controller is configured to control a sequence in which the first and second clock signals are output by controlling when the first and second commands are output.

11. The clock management circuitry of claim 10, wherein

the first slave clock controller is configured to send the first acknowledgement to the first master clock controller via the first channel in response to the output of the first clock signal;

the second slave clock controller is configured to send the second acknowledgement to the first master clock controller via the second channel in response to an output of the second clock signal; and

the first master clock controller is configured to control an output of a third clock signal after receipt of the first and second acknowledgements.

12. The clock management circuitry of claim 1, wherein

the first slave clock controller is configured to receive a second clock request from a first hardware component via a third channel and is configured to control generating the first clock signal based on the first command and the second clock request;

and

the second slave clock controller is configured to receive a third clock request from a second hardware component via a fourth channel and is configured to control generating the second clock signal based on the second command and the third clock request.

13. The clock management circuitry of claim 1, wherein

the first slave clock controller is configured to receive the first clock request, and the first slave clock controller is configured to control generating the first clock signal in response to at least one of the first clock request and the first command;

and

the second slave clock controller is configured to receive the first clock request, and the second slave clock controller is configured to control generating the second clock signal in response to at least one of the first clock request and the second command.

14. A system on chip, comprising:

at least first and second hardware components; and

clock management circuitry configured to control supply of a first clock and a second clock to the first and second hardware components, respectively, the clock management circuitry including a first slave clock controller, a second slave clock controller, and a first master clock controller, the first master clock controller configured to (1) provide a first command to the first slave clock controller via a first channel and a second command to the second slave clock controller via a second channel, based on a first clock request, (2) control operation of the first slave clock controller to control supply of the first clock based on the first command, and (3) control operation of the second slave clock controller to control supply of the second clock based on the second command,

wherein the first master clock controller is configured to control the second slave clock controller after receiving a first acknowledgement from the first slave clock controller, and

the first master clock controller is configured to perform a clock gating operation after receiving the first acknowledgement indicating that the first slave clock controller has completed a controlling operation with respect to the supply of the first clock, and a second acknowledgement indicating that the second slave clock controller has completed a controlling operation with respect to the supply of the second clock.

15. The system on chip of claim 14, wherein

the second hardware component is on a communication path with the first hardware component;

and

the first master clock controller is further configured to control the first slave clock controller to supply the second clock before the first master clock controller supplies the first clock.

16. The system on chip of claim 15, further comprising:

a third hardware component; and

wherein the second slave clock controller is configured to control supply of a third clock to the third hardware component.

17. The system on chip of claim 16, wherein

the second hardware component and the third hardware component are on the communication path with the first hardware component;

and

the first master clock controller is configured to control the first and second slave clock controllers to supply the second and third clocks before the first master clock controller supplies the first clock, and supply the second and third clocks in a sequence based on an order of the second and third hardware components along the communication path.

18. The system on chip of claim 16, wherein

the first master clock controller is configured to send the first command to the first slave clock controller via the first channel and send the second command to the second slave clock controller via the second channel.

19. A method of clock management, comprising:

providing a first clock request by a first master clock controller to a first slave clock controller;

supplying a first command to the first slave clock controller via a first channel based on the first clock request provided by the first master clock controller, the first slave clock controller configured to control an output of a first clock based on the first command;

receiving a first acknowledgement from the first slave clock controller, the first acknowledgement indicating the output of the first clock;

providing a second command to a second slave clock controller via a second channel based on the first clock request provided by the first master clock controller after receiving the first acknowledgement;

controlling an output of a second clock based on the second command; and

performing a clock gating operation by the first master clock controller after receiving the first acknowledgement indicating that the first slave clock controller has completed a controlling operation with respect to the output of the first clock, and a second acknowledgement indicating that the second slave clock controller has completed a controlling operation with respect to the output of the second clock.