Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
First Claim
1. A memory controller for performing error correction, comprising:
- I/O (input/output) hardware coupled to an associated memory device to send a read command to the associated memory device, the read command including a request that internal check bits be returned with read data, to cause the associated memory device to perform internal error detection to detect errors in read data, selectively perform an internal error correction operation on the read data in response to detection of an error in read data, and generate check bits indicating an error vector for the read data after performance of internal error detection and correction; and
the I/O hardware to receive the check bits with the read data in response to the read command; and
an error correction circuit to access the check bits for system error correction external to the associated memory device.
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Accused Products
Abstract
Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.
40 Citations
18 Claims
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1. A memory controller for performing error correction, comprising:
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I/O (input/output) hardware coupled to an associated memory device to send a read command to the associated memory device, the read command including a request that internal check bits be returned with read data, to cause the associated memory device to perform internal error detection to detect errors in read data, selectively perform an internal error correction operation on the read data in response to detection of an error in read data, and generate check bits indicating an error vector for the read data after performance of internal error detection and correction; and
the I/O hardware to receive the check bits with the read data in response to the read command; andan error correction circuit to access the check bits for system error correction external to the associated memory device. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system comprising:
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multiple memory devices; and a memory controller coupled to the memory devices, the memory controller including I/O (input/output) hardware coupled to the memory devices to send a read command to a selected memory device, the read command including a request that internal check bits be returned with read data, to cause the selected memory device to perform internal error detection to detect errors in read data, selectively perform an internal error correction operation on the read data in response to detection of an error in read data, and generate check bits indicating an error vector for the read data after performance of internal error detection and correction; and
the I/O hardware to receive the check bits with the read data in response to the read command. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method for error correction in a memory subsystem, comprising:
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generating a read command for an associated memory device, the read command including a request that internal check bits be returned with read data; sending the read command to the associated memory device, to cause the associated memory device to perform internal error detection to detect errors in read data, selectively perform an internal error correction operation on the read data in response to detection of an error in read data, and generate check bits indicating an error vector for the read data after performance of internal error detection and correction; receiving the check bits with the read data in response to the read command; and accessing the check bits for system error correction external to the associated memory device. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification