Package structure with bump

• US 10,515,899 B2
• Filed: 10/03/2016
• Issued: 12/24/2019
• Est. Priority Date: 10/03/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiu, Ming-Yen, Huang, Hsin-Chieh, Chang, Ching-Fu
• Primary Examiner(s): Tornow, Mark W
• Assistant Examiner(s): Boyle, Abbigale A
• Application Number:
  US15/284,425
• Publication Number:
  US 20180096939A1
• Time in Patent Office: 1,177 Days
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13026 relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package structure includes a redistribution layer in the passivation layer. The package structure also includes first bumps electrically connected to the integrated circuit chip through the redistribution layer. The first bumps are inside the chip edge and arranged along the chip edge. The package structure further includes second bumps electrically connected to the integrated circuit chip through the redistribution layer. The second bumps are outside the chip edge and arranged along the chip edge. The first bumps are next to the second bumps. The first and second bumps are spaced apart from the chip edge.

Claims

1. A package structure, comprising:

a molding compound;

an integrated circuit chip in the molding compound, wherein the integrated circuit chip has a chip edge and, in plan view, exhibits a footprint, an outer periphery of which corresponds to the chip edge;

a passivation layer below the integrated circuit chip and the molding compound;

a redistribution layer in the passivation layer; and

first bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the first bumps are, in plan view, within the footprint and arranged along a first direction;

second bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the second bumps are, in plan view, outside of the footprint and arranged along the first direction, and the first bumps and the second bumps are spaced apart from the chip edge; and

a second integrated circuit chip having a second chip edge in the molding compound, wherein, in plan view, the second integrated circuit chip exhibits a second footprint, an outer periphery of which corresponds to the second chip edge, wherein the second bumps are, in plan view, outside of the footprint and outside of the second footprint, and none of the second bumps is arranged between the chip edge and the second chip edge, and

wherein the first bumps are adjacent to the chip edge and spaced apart from each other by a first distance along the first direction, one of the first bumps and one of the second bumps are directly adjacent to each other and spaced apart from each other by a second distance along the first direction, and wherein the second distance is greater than the first distance.

2. The package structure as claimed in claim 1, wherein the first bumps are spaced apart from the chip edge by a third distance, and the second bumps are spaced apart from the chip edge by a fourth distance, and wherein each of the third distance and the fourth distance is in a range from about 15 μ

m to about 100 μ

m.

3. The package structure as claimed in claim 1, wherein the first bumps are spaced apart from the chip edge by a third distance, and the second bumps are spaced apart from the chip edge by a fourth distance that is different from the third distance.

4. The package structure as claimed in claim 1, further comprising:

first under-bump metallurgy (UBM) elements between the redistribution layer and the first bumps and arranged along the chip edge; and

second UBM elements between the redistribution layer and the second bumps and arranged along the chip edge, wherein none of the first and second UBM elements overlaps the chip edge.

5. The package structure as claimed in claim 1, wherein an interval between the chip edge and the second chip edge is less than a first bump pitch between the first bumps or a second bump pitch between the second bumps.

6. A package structure, comprising:

a package layer;

an integrated circuit chip in the package layer, wherein the integrated circuit chip has a chip edge, which in plan view defines an outer periphery of the integrated circuit chip;

a passivation layer below the integrated circuit chip and the package layer, wherein the passivation layer comprises a first region and a second region adjoining the first region, and a boundary between the first and second regions, and wherein the boundary, in plan view, is substantially aligned to the chip edge;

a redistribution layer in the passivation layer, wherein the redistribution layer extends across the boundary;

first bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the first bumps are in the first region;

a second integrated circuit chip having a second chip edge, which in plan view defines an outer periphery of the second integrated circuit chip, in the package layer; and

second bumps electrically connected to the integrated circuit chip through the redistribution layer, wherein the second bumps are in the second region, the first bumps and the second bumps are directly adjacent to the boundary and arranged along the boundary without overlapping the boundary, and

wherein one of the second bumps is directly adjacent to the chip edge and the second chip edge and is spaced apart from the chip edge and the second chip edge by different distances, and wherein two of the first bumps and the one of the second bumps are collinear, the two of the first bumps are spaced apart from each other by a first distance, and a minimum distance between the one of the second bumps and the two of the first bumps is greater than the first distance.

7. The package structure as claimed in claim 6, wherein center points of the two of the first bumps and center points of the one of the second bumps are collinear in a direction perpendicular to the boundary.

8. The package structure as claimed in claim 6, wherein another one of the second bumps is entirely within the outer periphery of the second integrated circuit chip and directly adjacent to the one of the second bumps.

9. The package structure as claimed in claim 6, wherein the first bumps are spaced apart from the boundary by a first boundary distance, and the second bumps are spaced apart from the boundary by a second boundary distance, and wherein the first and second distances are in a range from about 15 μ

m to about 100 μ

m.

10. The package structure as claimed in claim 6, wherein another two of the first bumps are spaced apart from the boundary by different distances.

11. The package structure as claimed in claim 6, further comprising:

first under-bump metallurgy (UBM) elements between the redistribution layer and the first bumps in the first region; and

second UBM elements between the redistribution layer and the second bumps in the second region, wherein the first UBM elements and the second UBM elements are spaced apart from the boundary.

12. The package structure as claimed in claim 6, wherein no bump, in plan view, overlaps the second chip edge.

13. The package structure as claimed in claim 6, wherein the package structure is bonded to a circuit board comprising conductive pads through the first and second bumps, and the conductive pads are next to the boundary and misaligned to the boundary.

14. The package structure as claimed in claim 13, wherein the first and second bumps between the circuit board and the passivation layer, in plan view, do not cross the chip edge, and wherein the second bumps are outside of a first footprint of the integrated circuit chip and a second footprint of the second integrated circuit chip.

19. The package structure as claimed in claim 6, wherein one of the first bumps and one of the second bumps which are directly adjacent to each other have a distance and a bump pitch therebetween, and a ratio of the distance to the bump pitch is in a range from 0.1 to 0.15.

15. A package structure, comprising:

a package layer;

a first chip in the package layer, wherein the first chip has a first chip edge, which in plan view defines a portion of an outer periphery of the first chip;

a second chip in the package layer, wherein the second chip has a second chip edge, which in plan view defines a portion of an outer periphery of the second chip, facing the first chip edge, and wherein an interval is defined between the first chip edge and the second chip edge;

a passivation layer below the first chip, the second chip and the package layer;

redistribution lines in the passivation layer; and

bumps electrically connected to the first chip and the second chip through the redistribution lines, wherein the bumps comprise;

first bumps arranged, in plan view, adjacent to the first chip edge and within the outer periphery of the first chip;

second bumps arranged, in plan view, adjacent to the second chip edge and within the outer periphery of the second chip; and

third bumps arranged, in plan view, outside the outer periphery of the first chip and outside the outer periphery of the second chip, wherein a bump pitch is defined between one of the first bumps and one of the third bumps that are directly adjacent to each other,

wherein the interval is less than the bump pitch, and the third bumps are arranged outside a region between the first and second chip edges to partially surround the first and second chip edges.

16. The package structure as claimed in claim 15, wherein the third bumps are directly adjacent to the first chip edge and spaced apart from the first chip edge by a distance in a range from about 15 μ

m to about 100 μ

m.

17. The package structure as claimed in claim 15, wherein one of the first bumps and one of the third bumps that are directly adjacent to each other are separated by a distance in a range from about 30 μ

m to about 200 μ

m.

18. The package structure as claimed in claim 15, wherein:

the package structure further comprises a first interface between the first chip and the package layer, and a second interface between the second chip and the package layer; and

the first bumps, the second bumps, and the third bumps are not directly under the first interface, and the first bumps, the second bumps, and the third bumps are not directly under the second interface.

20. The package structure as claimed in claim 15, wherein in plan view, the outer periphery of the first chip has a first side facing a second side of the outer periphery of the second chip, and there are no bumps arranged between the first side and the second side.