System power management using communication bus protocols

• US 10,551,907 B2
• Filed: 06/16/2016
• Issued: 02/04/2020
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Warren, David S., Levit, Inna, Paaske, Timothy R.
• Primary Examiner(s): Nguyen, Phil K
• Assistant Examiner(s): Sampath, Gayathri
• Application Number:
  US15/184,190
• Publication Number:
  US 20160291685A1
• Time in Patent Office: 1,328 Days
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Claims

1. An apparatus, comprising:

a host device; and

an endpoint device coupled to the host device via a communication bus, wherein the endpoint device includes;

one or more functional circuit blocks configured to operate in a first power mode and a second power mode, wherein a power dissipation of the one or more functional circuit blocks is less in the second power mode than the first power mode; and

a control circuit coupled to the one or more functional circuit blocks, wherein the control circuit is configured to;

monitor a level of activity of the one or more functional circuit blocks operating in the first power mode;

in response to detecting a particular level of activity of the one or more functional circuit blocks, send a message to the host device, wherein the message includes data indicative of a time for the one or more functional circuit blocks to resume operation after exiting the second power mode;

send, to the host device via the communication bus, a request to activate the second power mode for the one or more functional circuit blocks; and

receive, from the host device via the communication bus, a response to the request to activate the second power mode; and

wherein the host device is configured to generate the response in response to a determination whether the one or more functional circuit blocks can enter the second power mode wherein the determination is made using the data included in the message.

2. The apparatus of claim 1, wherein to activate the second power mode, the control circuit is further configured to reduce a voltage level of a power supply coupled to at least one of the one or more functional circuit blocks.

3. The apparatus of claim 1, further comprising a clock generation circuit configured to generate at least one clock signal, wherein the clock signal is coupled to at least one of the one or more functional circuit blocks, and wherein to activate the second power mode, the control circuit is further configured to deactivate the at least one clock signal.

4. The apparatus of claim 1, wherein the data indicative of the time to for the one or more functional circuit blocks to return to respective states to perform their respective functions after exiting the second power mode includes a scale value.

5. The apparatus of claim 1, further comprising an interface unit coupled to the communication bus, and wherein to activate the second power mode, the control circuit is further configured to deactivate the interface unit.

6. The apparatus of claim 1, further comprising a clock generation circuit that includes a phase-locked loop (PLL).

7. A method, comprising:

monitoring, by a control circuit included in a first device included in a computer system, a level of activity of one or more functional circuit blocks included in the first device, wherein the one or more functional circuit blocks are operating in a first power mode;

in response to detecting, by the control circuit, a particular level of activity of the one or more functional circuit blocks operating in the first power mode, sending, by the first device, a message to a second device included in the computing system via a communication bus, wherein the message includes data indicative of a time to resume operation after exiting a second power mode, and wherein power dissipation of the one or more functional circuit blocks is less in the second power mode than the first power mode;

sending, by the first device to the second device, a request to activate the second power mode for the first device;

generating, by the second device, a response to the request to activate the second power mode, in response to determining, using the data included in the message, whether the second device can enter the second power mode; and

receiving, from the second device by the first device via the communication bus, a response to the request to activate the second power mode.

8. The method of claim 7, wherein activating the second power mode includes reducing a voltage level of a power supply coupled to at least one of the one or more functional circuit blocks.

9. The method of claim 7, wherein activating the second power mode includes deactivating at least one clock signal that is coupled to at least one of the one or more functional circuit blocks.

10. The method of claim 7, wherein the data indicative of the time to resume operation after activation of the second power mode includes a scale value.

11. The method of claim 10, further comprising comparing the data indicative of the time to a fully powered state to a plurality of threshold values.

12. The method of claim 11, wherein the response includes information indicative of a power mode that the first device is to activate.

13. The method of claim 7, wherein to activating the second power mode includes deactivating an interface unit included in the computing system.

14. A system, comprising:

a host; and

a device coupled to the host via a communication bus, wherein the device is configured to;

operate in a first power mode and a second power mode, wherein a power dissipation of the device is less in the second power mode than the first power mode;

monitor a level of activity of the device while operating in the first power mode;

in response to detecting a particular level of activity of the device while operating in the first power mode, send, via the communication bus, a message to the host that includes data indicative of a time to resume operation after exiting the second power mode; and

send, to the host via the communication bus, a request to active the second power mode; and

receive, from the host via the communication bus, a response to the request to activate the second power mode; and

wherein the host is configured to generate, using the data included in the message, the response in response to a determination whether the device can enter the second power mode.

15. The system of claim 14, wherein the device includes one or more functional circuit blocks, and wherein to activate the second power mode, the device is further configured to reduce a voltage level of a power supply coupled to at least one of the one or more functional circuit blocks.

16. The system of claim 14, wherein the device includes one or more functional circuit blocks that includes a clock generation circuit configured to generate at least one clock signal coupled to at least one of the one or more functional circuit blocks, and wherein to activate the second power mode, the device is further configured to deactivate the at least one clock signal.

17. The system of claim 16, wherein the clock generation circuit includes a phase-locked loop (PLL).

18. The system of claim 14, wherein the data indicative of the time to resume operation after activation of the second power mode includes a scale value.

19. The system of claim 18, wherein the device includes an interface unit coupled to the communication bus, and wherein to activate the second power mode, the device is further configured to deactivate the interface unit.

20. The system of claim 18, wherein to generate the response, the host is configured to generate the response using the data indicative of the time to resume operation after exiting the second power mode and the scale value.