Array substrate and display panel

• US 10,564,745 B2
• Filed: 06/06/2016
• Issued: 02/18/2020
• Est. Priority Date: 02/05/2016
• Status: Active Grant

• Current Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Original Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Inventors: Du, Lingxiao, Yang, Kang, Ding, Hong, Li, Gujun, Liu, Shaofan
• Primary Examiner(s): Patel, Nitin
• Assistant Examiner(s): Stone, Robert M
• Application Number:
  US15/173,960
• Publication Number:
  US 20170228074A1
• Time in Patent Office: 1,352 Days
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/133514 Colour filters
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G06F 2203/04111 Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

The present disclosure provides an array substrate including a display region and a frame region surrounding the display region. The display region further includes a plurality of second touch lines which are in parallel with the gate electrode lines, and each of the common electrode units is electrically connected to one of the second touch lines through a via hole. The frame region consists of a plurality of first switches and a plurality of test lines extending along a second direction, at least one end of each second touch line is connected to one of the first switches, and the test lines are electrically connected to the first switches.

Claims

1. An array substrate comprising a display region and a frame region surrounding the display region, wherein:

the display region consists of a common electrode layer, a touch line layer, a gate electrode layer, and a plurality of second touch lines which are in parallel with the gate electrode lines, wherein

the common electrode layer comprises a plurality of common electrode units,

the touch line layer comprises a plurality of first touch lines electrically connected to the common electrode units, and

the gate electrode layer comprises a plurality of gate electrode lines extending along a first direction, and

each of the common electrode units is electrically connected to one of the second touch lines through a via hole, wherein each of the common electrode units are electrically connected to one of the plurality of first touch lines, and the plurality of first touch lines extend along a second direction, and the first touch line and the second touch line connected to one common electrode are extended along different direction and are intersected while not interconnected; and

the frame region consists of a plurality of first switches and a plurality of test lines extending along the second direction, wherein at least one end of each second touch line is connected to one of the first switches, and the test lines are electrically connected to the first switches.

2. The array substrate of claim 1, wherein the second touch lines and the gate electrode lines are positioned at a same layer.

3. The array substrate of claim 2, wherein two ends of each second touch line are respectively electrically connected to one of the first switches.

4. The array substrate of claim 2 wherein the first touch lines are electrically connected to the common electrode units through via holes.

5. The array substrate of claim 2, wherein the first touch lines are extended along the second direction.

6. The array substrate of claim 5, wherein the first direction is a direction along which a shorter side of the array substrate is extended, and the second direction is a direction along which a longer side of the array substrate is extended.

7. The array substrate of claim 1, wherein the second direction is perpendicular to the first direction.

8. The array substrate of claim 7, wherein

the first switches are thin film transistors;

one end of each second touch line is electrically connected to a first electrode of one of the thin film transistors; and

the test lines are electrically connected to second electrodes of one of the thin film transistors.

9. The array substrate of claim 8, wherein the array substrate further comprises at least one test control line electrically connected to control terminals of the thin film transistors.

10. The array substrate of claim 9, wherein

the test lines comprise a first test line and a second test line, and the common electrode units are arranged successively along the first direction and the second direction;

the common electrode units in odd numbers of columns are electrically connected to the first test line through the thin film transistors; and

the common electrode units in even numbers of columns are electrically connected to the second test line through the thin film transistors.

11. The array substrate of claim 9, wherein

the test lines comprise a first test line and a second test line, and the common electrode units are arranged successively along the first direction and the second direction;

the common electrode units in odd numbers of columns and odd numbers of rows and the common electrode units in even numbers of columns and even numbers of rows are electrically connected to the first test line through the thin film transistors; and

the common electrode units in odd numbers of columns and even numbers of rows and the common electrode units in even numbers of columns and odd numbers of rows are electrically connected to the second test line through the thin film transistors.

12. The array substrate of claim 9 wherein in a test stage, the thin film transistors are in turned-on states, and the first test line inputs a different voltage from a voltage input by the second test line.

13. The array substrate of claim 9 wherein in a display stage, the test control line controls the thin film transistors into turned-on states, the first test line and the second test line input common electrode signals, and the common electrode units are short circuited.

14. The array substrate of claim 9 wherein in a touch stage, the test control line controls the thin film transistors into turned-off states.

15. The array substrate of claim 8, wherein

the frame region comprises a first frame sub-region and a second frame sub-region respectively distributed at two sides of the display region along the first direction;

the thin film transistors are positioned in the first frame sub-region and/or the second frame sub-region; and

at least part of the test lines is positioned in the first frame sub-region and/or the second frame sub-region.

16. The array substrate of claim 7, wherein the common electrode units are used as common electrodes in a display stage, and used as driving touch electrodes or sensing touch electrodes in a touch stage.

17. The array substrate of claim 7, wherein the common electrode units are used as common electrodes in a display stage, and used as self-capacitive touch electrodes in a touch stage.

18. The array substrate of claim 1 wherein the frame region consists of a touch control IC, and the first touch lines and the second touch lines are electrically connected to the touch control IC.

19. The array substrate of claim 18, wherein the frame region further comprises a third frame sub-region and a fourth frame sub-region respectively distributed at two sides of the display region along the second direction, and the touch control IC is positioned in the third frame sub-region or the fourth frame sub-region.

20. A display panel comprising an array substrate and a color film substrate disposed oppositely to each other, and a liquid crystal layer between the array substrate and the color film substrate, wherein the array substrate comprising:

a display region and a frame region surrounding the display region, wherein;

the display region consists of a common electrode layer, a touch line layer, a gate electrode layer, and a plurality of second touch lines which are in parallel with the gate electrode lines, wherein

the common electrode layer comprises a plurality of common electrode units,

the touch line layer comprises a plurality of first touch lines electrically connected to the common electrode units, and

the gate electrode layer comprises a plurality of gate electrode lines extending along a first direction, and

each of the common electrode units is electrically connected to one of the second touch lines through a via hole, wherein each of the common electrode units are electrically connected to one of the plurality of first touch lines, and the plurality of first touch lines extend along a second direction, and the first touch line and the second touch line connected to one common electrode are extended along different direction and are intersected while not interconnected; and

the frame region consists of a plurality of first switches and a plurality of test lines extending along the second direction, wherein at least one end of each second touch line is connected to one of the first switches, and the test lines are electrically connected to the first switches.