Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
First Claim
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1. An apparatus comprising:
- a logic circuit configured to responsive to first information to provide second information,wherein the first information comprises a first plurality of bits, less significant bits of the first information including first, second, third and fourth bits, the first bit being a least significant bit of the first plurality of bits;
wherein the second information comprises a second plurality of bits, less significant bits of the second information comprising fifth, sixth, seventh and eighth bits, the fifth bit being a least significant bit of the second plurality of bits;
wherein the logic circuit is further configured;
to perform a logical inversion on the first bit to provide the fifth bit,to perform a first logical operation on first, second, third and fourth bits to provide the sixth bit,to perform a second logical operation on first, second, third and fourth bits to provide the seventh bit, andto perform a third logical operation on first, second, third and fourth bits to provide the eighth bit; and
wherein the first, second and third logical operations are different from one another.
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Abstract
An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
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Citations
20 Claims
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1. An apparatus comprising:
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a logic circuit configured to responsive to first information to provide second information, wherein the first information comprises a first plurality of bits, less significant bits of the first information including first, second, third and fourth bits, the first bit being a least significant bit of the first plurality of bits; wherein the second information comprises a second plurality of bits, less significant bits of the second information comprising fifth, sixth, seventh and eighth bits, the fifth bit being a least significant bit of the second plurality of bits; wherein the logic circuit is further configured; to perform a logical inversion on the first bit to provide the fifth bit, to perform a first logical operation on first, second, third and fourth bits to provide the sixth bit, to perform a second logical operation on first, second, third and fourth bits to provide the seventh bit, and to perform a third logical operation on first, second, third and fourth bits to provide the eighth bit; and wherein the first, second and third logical operations are different from one another. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
an address scrambler circuit comprising a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address, wherein the sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, wherein the sub-wordline scrambler circuit is further configured to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method comprising:
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receiving a first subset of bits of a row hammer hit address at an address scrambler circuit; performing a first set of logical operations on the first subset of bits to provide a second subset of bits; and performing a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of a row hammer refresh address. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification