Sloped finFET with methods of forming same

• US 10,629,703 B2
• Filed: 01/11/2018
• Issued: 04/21/2020
• Est. Priority Date: 02/06/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Brent A., Nowak, Edward J.
• Primary Examiner(s): Kim, Tong-Ho
• Application Number:
  US15/868,224
• Publication Number:
  US 20180138286A1
• Time in Patent Office: 831 Days
• Field of Search: 257347, 438586
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Claims

1. An integrated circuit (IC) structure comprising:

a semiconductor fin formed over an insulator layer, the semiconductor fin including;

a first region including substantially vertical sidewalls;

a second region formed adjacent the first region; and

a third region formed adjacent to the second region, and separated from the first region via the second region, the third region including sloped sidewalls;

a gate dielectric positioned above the first region of the semiconductor fin;

a spacer positioned above the second region of the semiconductor fin and adjacent to the gate dielectric; and

a source/drain region directly contacting the sloped sidewalls of the third region of the semiconductor fin;

wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

2. The IC structure of claim 1, wherein the sloped sidewalls of the third region are oriented at an angle of between approximately seventy degrees and approximately eighty-seven degrees relative to an insulator layer positioned beneath the IC structure.

3. The IC structure of claim 1, wherein the second region of the semiconductor fin includes sloped sidewalls.

4. The IC structure of claim 3, wherein the sloped sidewalls of the second region are oriented at an angle of between approximately seventy degrees and approximately eighty-seven degrees relative to an insulator layer positioned beneath the IC structure.

5. The IC structure of claim 1, wherein a height of first region is less than a height of the third region.

6. The IC structure of claim 1, wherein a width of the semiconductor fin in the first region is less than approximately half of a width of the semiconductor fin in the third region.

7. The IC structure of claim 1, wherein the spacer is positioned circumferentially about the gate dielectric.

8. The IC structure of claim 1, further comprising a plurality of semiconductor fins extending through the gate dielectric and the spacer, wherein one of the plurality of semiconductor fins includes sloped sidewalls.

9. The IC structure of claim 1, wherein the spacer includes a first spacer positioned circumferentially about the gate dielectric, and a second spacer positioned circumferentially about the first spacer.

10. An integrated circuit (IC) structure comprising:

a semiconductor fin formed over an insulator layer, the semiconductor fin including;

two end regions including sloped sidewalls; and

a channel region positioned between the two end regions, the channel region including substantially vertical sidewalls;

a gate dielectric positioned above the channel region of the semiconductor fin;

a spacer positioned above at least a portion of each of the two end regions of the semiconductor fin, the spacer positioned circumferentially about the gate dielectric;

a source contact coupled directly to the sloped sidewalls of one of the two end regions of the semiconductor fin; and

a drain contact coupled directly to the sloped sidewalls of the other of the two end regions of the semiconductor fin.

11. The IC structure of claim 10, wherein the two end regions include sidewalls oriented at an angle of between approximately seventy degrees and approximately eighty-seven degrees relative to an insulator layer positioned beneath the IC structure.

12. The IC structure of claim 10, wherein a height of the channel region is less than a height of the two end regions.

13. The IC structure of claim 10, wherein a width of the semiconductor fin in the channel region is less than approximately half of a width of the semiconductor fin in the two end regions.

14. The IC structure of claim 10, further comprising a plurality of semiconductor fins extending through the gate dielectric and the spacer, wherein one of the plurality of semiconductor fins includes sloped sidewalls.

15. The IC structure of claim 10, wherein the spacer includes a first spacer positioned circumferentially about the gate dielectric, and a second spacer positioned circumferentially about the first spacer.

16. An integrated circuit (IC) structure comprising:

a semiconductor fin formed over an insulator layer, the semiconductor fin including;

a first region including substantially vertical sidewalls;

a second region formed adjacent the first region; and

a third region formed adjacent the second region, and separated from the first region via the second, the third region including sloped sidewalls;

a gate dielectric positioned above the first region of the semiconductor fin;

a first spacer positioned above the second region of the semiconductor fin, the first spacer positioned circumferentially about the gate dielectric;

a second spacer positioned circumferentially about the first spacer; and

a source/drain region directly contacting the sloped sidewalls of the third region of the semiconductor fin.

17. The IC structure of claim 16, wherein the sloped sidewalls of the third region are oriented at an angle of between approximately seventy degrees and approximately eighty-seven degrees relative to an insulator layer positioned beneath the IC structure.

18. The IC structure of claim 16, wherein sloped sidewalls of the second region are oriented at an angle of between approximately seventy degrees and approximately eighty-seven degrees relative to an insulator layer positioned beneath the IC structure.

19. The IC structure of claim 16, wherein a height of first region is less than a height of the third region.

20. The IC structure of claim 16, wherein a width of the semiconductor fin in the first region is less than approximately half of a width of the semiconductor fin in the third region.