Sloped finFET with methods of forming same
First Claim
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1. An integrated circuit (IC) structure comprising:
- a semiconductor fin formed over an insulator layer, the semiconductor fin including;
a first region including substantially vertical sidewalls;
a second region formed adjacent the first region; and
a third region formed adjacent to the second region, and separated from the first region via the second region, the third region including sloped sidewalls;
a gate dielectric positioned above the first region of the semiconductor fin;
a spacer positioned above the second region of the semiconductor fin and adjacent to the gate dielectric; and
a source/drain region directly contacting the sloped sidewalls of the third region of the semiconductor fin;
wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.
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Abstract
Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.
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Citations
20 Claims
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1. An integrated circuit (IC) structure comprising:
a semiconductor fin formed over an insulator layer, the semiconductor fin including; a first region including substantially vertical sidewalls; a second region formed adjacent the first region; and a third region formed adjacent to the second region, and separated from the first region via the second region, the third region including sloped sidewalls; a gate dielectric positioned above the first region of the semiconductor fin; a spacer positioned above the second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region directly contacting the sloped sidewalls of the third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit (IC) structure comprising:
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a semiconductor fin formed over an insulator layer, the semiconductor fin including; two end regions including sloped sidewalls; and a channel region positioned between the two end regions, the channel region including substantially vertical sidewalls; a gate dielectric positioned above the channel region of the semiconductor fin; a spacer positioned above at least a portion of each of the two end regions of the semiconductor fin, the spacer positioned circumferentially about the gate dielectric; a source contact coupled directly to the sloped sidewalls of one of the two end regions of the semiconductor fin; and a drain contact coupled directly to the sloped sidewalls of the other of the two end regions of the semiconductor fin. - View Dependent Claims (11, 12, 13, 14, 15)
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16. An integrated circuit (IC) structure comprising:
a semiconductor fin formed over an insulator layer, the semiconductor fin including; a first region including substantially vertical sidewalls; a second region formed adjacent the first region; and a third region formed adjacent the second region, and separated from the first region via the second, the third region including sloped sidewalls; a gate dielectric positioned above the first region of the semiconductor fin; a first spacer positioned above the second region of the semiconductor fin, the first spacer positioned circumferentially about the gate dielectric; a second spacer positioned circumferentially about the first spacer; and a source/drain region directly contacting the sloped sidewalls of the third region of the semiconductor fin. - View Dependent Claims (17, 18, 19, 20)
Specification