AC coupling modules for bias ladders
First Claim
1. A method for providing a FET switch stack, including:
- (a) providing a plurality of series-coupled FETs, including a first end FET having a first signal terminal and a second end FET having a second signal terminal, wherein the plurality of series-coupled FETs includes one or more series-coupled positive-logic FETs requiring a relative negative VGS to turn OFF but configured to not require a negative power supply, and a first end-cap FET that turns OFF when the VGS of such first end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs;
(b) coupling a gate bias resistor ladder to the gates of the series-coupled FETs, the gate bias resistor ladder configured to be coupled to a gate control voltage that controls the ON or OFF switch state of each series-coupled FET; and
(c) coupling an AC coupling gate module to at least one end of the gate bias resistor ladder and configuring the AC coupling gate module to be coupled to a radio frequency voltage source;
wherein in response to the OFF switch state of each series-coupled FET, a signal applied to the first or second signal terminal is blocked from conduction through the plurality of series-coupled FETs, and wherein in response to the ON switch state of each series-coupled FET, a signal applied to the first or second signal terminal is conducted through the plurality of series-coupled FETs.
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Abstract
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
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Citations
16 Claims
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1. A method for providing a FET switch stack, including:
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(a) providing a plurality of series-coupled FETs, including a first end FET having a first signal terminal and a second end FET having a second signal terminal, wherein the plurality of series-coupled FETs includes one or more series-coupled positive-logic FETs requiring a relative negative VGS to turn OFF but configured to not require a negative power supply, and a first end-cap FET that turns OFF when the VGS of such first end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs; (b) coupling a gate bias resistor ladder to the gates of the series-coupled FETs, the gate bias resistor ladder configured to be coupled to a gate control voltage that controls the ON or OFF switch state of each series-coupled FET; and (c) coupling an AC coupling gate module to at least one end of the gate bias resistor ladder and configuring the AC coupling gate module to be coupled to a radio frequency voltage source; wherein in response to the OFF switch state of each series-coupled FET, a signal applied to the first or second signal terminal is blocked from conduction through the plurality of series-coupled FETs, and wherein in response to the ON switch state of each series-coupled FET, a signal applied to the first or second signal terminal is conducted through the plurality of series-coupled FETs. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for providing a FET switch stack, including:
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(a) providing a plurality of series-coupled FETs, wherein the plurality of series-coupled FETs includes one or more series-coupled positive-logic FETs requiring a relative negative VGS to turn OFF but configured to not require a negative power supply, and a first end-cap FET that turns OFF when the VGS of such first end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs; (b) coupling a gate bias resistor ladder to the gates of the series-coupled FETs; (c) coupling an AC coupling gate module to at least one end of the gate bias resistor ladder and configuring the AC coupling gate module to be coupled to a corresponding radio frequency voltage source; (d) coupling a body charge control resistor ladder to the bodies of the series-coupled FETs; and (e) coupling an AC coupling body module to at least one end of the body charge control resistor ladder and configuring the AC coupling body module to be coupled to the corresponding radio frequency voltage source. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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Specification