Partially de-centralized latch management architectures for storage devices
First Claim
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1. A memory system comprising:
- a controller;
non-volatile memory coupled with the controller, wherein the non-volatile memory further comprises;
a non-volatile memory array comprising a plurality of dies;
latches that are located on the dies; and
latch management circuitry that dynamically identifies any one of the plurality dies as a leader die, wherein;
any of the plurality of dies can be identified as the leader die, andthe leader die performs a data transfer to or from one or more latches from one of the dies.
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Abstract
A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.
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Citations
22 Claims
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1. A memory system comprising:
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a controller; non-volatile memory coupled with the controller, wherein the non-volatile memory further comprises; a non-volatile memory array comprising a plurality of dies; latches that are located on the dies; and latch management circuitry that dynamically identifies any one of the plurality dies as a leader die, wherein; any of the plurality of dies can be identified as the leader die, and the leader die performs a data transfer to or from one or more latches from one of the dies. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A memory system comprising:
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a controller; a non-volatile memory coupled with the controller, the non-volatile memory comprising; a plurality of memory dies, wherein each of the memory dies comprises;
cache storage for storing data, andany one of the memory dies can be dynamically identified as a leader die; and caching logic circuitry configured to be used by the leader die to; manage a subset of the cache storage for a subset of the memory dies, wherein the subset of the memory dies are connected with the leader die, and dynamically identify a cache storage of the subset of the cache storage to use for a data transfer, wherein any cache storage of the subset of the cache storage can be chosen for data transfer. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A memory device with a controller and NAND memory, the device comprising:
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means for dynamically identifying any one of a plurality of dies in the NAND memory as a leader die, wherein any of the plurality of dies can be identified as the leader die; means for receiving a command that includes a data transfer to or from one or more latches of the plurality of dies in the NAND memory; and means for the leader die to manage the data transfer.
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Specification