Fabrication of logic devices and power devices on the same substrate
First Claim
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1. A method of forming a logic device and a power device on a substrate, comprising:
- forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region;
forming a first doped well in the substrate under the first vertical fin on the first region and a second doped well in the substrate under the second vertical fin on the second region;
forming a first bottom source/drain region in the first doped well under the first vertical fin on the first region, wherein a bottom source/drain region is not formed in the second doped well under the second vertical fin, andforming a dielectric under-layer segment on the second vertical fin on the second region;
forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region; and
forming a top source/drain on each of the first vertical fin and the second vertical fin, wherein the top source/drain on the second vertical fin is above the first gate structure.
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Abstract
A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.
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Citations
13 Claims
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1. A method of forming a logic device and a power device on a substrate, comprising:
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forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region; forming a first doped well in the substrate under the first vertical fin on the first region and a second doped well in the substrate under the second vertical fin on the second region; forming a first bottom source/drain region in the first doped well under the first vertical fin on the first region, wherein a bottom source/drain region is not formed in the second doped well under the second vertical fin, and forming a dielectric under-layer segment on the second vertical fin on the second region; forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region; and forming a top source/drain on each of the first vertical fin and the second vertical fin, wherein the top source/drain on the second vertical fin is above the first gate structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a logic device and a power device on a substrate, comprising:
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forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region; forming a first doped well in the substrate under the first vertical fin on the first region and a second doped well in the substrate under the second vertical fin on the second region; forming a bottom source/drain region in the first doped well, wherein a bottom source/drain region is not formed in the second doped well under the second vertical fin; forming a dielectric under-layer on the first vertical fin and the second vertical fin; forming a masking block on the dielectric under-layer and second vertical fin on the second region that leaves a portion of the dielectric under-layer on the first vertical fin exposed; removing the exposed portion of the dielectric under-layer to form a dielectric under-layer segment on the second vertical fin; removing the masking block; forming a gate dielectric layer on the dielectric under-layer segment and first vertical fin on the first region; and forming a top source/drain on a top surface of each of the first vertical fin and the second vertical fin. - View Dependent Claims (10, 11, 12, 13)
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Specification