Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods

• US 10,707,201 B2
• Filed: 11/21/2018
• Issued: 07/07/2020
• Est. Priority Date: 04/18/2014
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Fife, Keith G., Sanchez, Nevada J., Alie, Susan A.
• Primary Examiner(s): Yushina, Galina G
• Application Number:
  US16/197,438
• Publication Number:
  US 20190164956A1
• Time in Patent Office: 594 Days
• CPC Class Codes: A61B 8/00 Diagnosis using ultrasonic, sonic or infrasonic waves imaging of objects using sonar G01S15/00
• CPC Class Codes: A61B 8/4494 characterised by the arrangement of the transducer elements devices for short-range imaging using particular transducer elements arrangements under G01S15/8909; arrangements of transducers in generation of mechanical vibrations of infrasonic, sonic or ultrasonic frequency B06B1/0607
• CPC Class Codes: B06B 1/02 making use of electrical energy B06B1/18, B06B1/20 take precedence
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B06B 2201/51 Electrostatic transducer
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0617 : comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors

Abstract

Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

Claims

1. An ultrasound device, comprising:

a complementary metal oxide semiconductor (CMOS) wafer comprising;

an integrated circuit having a transistor gate layer;

a plurality of metallization layers disposed above the transistor gate layer; and

an ultrasonic transducer formed in the plurality of metallization layers above the transistor gate layer, the ultrasonic transducer comprising;

a bottom electrode formed above a first of the plurality of metallization layers;

a cavity disposed above the bottom electrode; and

a top electrode disposed above the cavity and formed below a second of the plurality of metallization layers;

wherein the top electrode comprises a plurality of vias disposed between the cavity and the second of the plurality of metallization layers.

2. The ultrasound device of claim 1, wherein the plurality of vias are spaced relative to each other by between approximately 0.1 microns and approximately 0.5 microns.

3. The ultrasound device of claim 1, wherein the plurality of vias are spaced relative to each other by between approximately 0.2 microns and approximately 0.3 microns.

4. The ultrasound device of claim 1, wherein the plurality of vias are each approximately 0.2 microns×

0.2 microns in cross-section.

5. The ultrasound device of claim 1, wherein the plurality of vias are each approximately 0.3 microns×

0.3 microns in cross-section.

6. The ultrasound device of claim 1, further comprising a third and a fourth of the plurality of metallization layers disposed between the first of the plurality of metallization layers and the transistor gate layer.

7. The ultrasound device of claim 1, wherein the integrated circuit is disposed directly beneath the ultrasonic transducer.

8. The ultrasound device of claim 1, wherein the second of the plurality of metallization layers is a topmost metallization layer of the plurality of metallization layers, and no metallization layers are disposed between the cavity and the second of the plurality of metallization layers.

9. The ultrasound device of claim 1, wherein the ultrasonic transducer further comprises an acoustic membrane that includes the top electrode and the second of the plurality of metallization layers.

10. The ultrasound device of claim 9, wherein the acoustic membrane further comprises a dielectric layer in which the second of the plurality of metallization layers is disposed.

11. The ultrasound device of claim 9, wherein the acoustic membrane further comprises:

a first passivation layer disposed over the second of the plurality of metallization layers; and

a second passivation layer disposed over the first passivation layer, the second passivation layer sealing access holes to the cavity.

12. The ultrasound device of claim 1, wherein the cavity comprises a void of a third of the plurality of metallization layers.

13. The ultrasound device of claim 12, wherein the ultrasonic transducer further comprises an acoustic membrane that includes:

the top electrode;

the second of the plurality of metallization layers;

a first dielectric layer in which the third of the plurality of metallization layers is disposed; and

a second dielectric layer in which the second of the plurality of metallization layers is disposed.

14. The ultrasound device of claim 1, wherein the plurality of metallization layers are configured as CMOS metallization layers for signal routing.

15. The ultrasound device of claim 1, further comprising sealed access holes to the cavity.

16. The ultrasound device of claim 12, wherein the sealed access holes are formed around a perimeter of the cavity and the plurality of metallization layers run between the sealed access holes.

17. An ultrasound device, comprising:

a complementary metal oxide semiconductor (CMOS) wafer comprising;

an integrated circuit having a transistor gate layer;

a plurality of metallization layers disposed above the transistor gate layer; and

an ultrasonic transducer formed in the plurality of metallization layers above the transistor gate layer, the ultrasonic transducer comprising;

a bottom electrode formed above a first of the plurality of metallization layers; and

a cavity disposed above the bottom electrode;

wherein the bottom electrode comprises a plurality of vias disposed between the first of the plurality of metallization layers and the cavity.

18. The ultrasound device of claim 17, wherein the plurality of metallization layers are configured as CMOS metallization layers for signal routing.

19. The ultrasound device of claim 17, further comprising a second and a third of the plurality of metallization layers disposed between the first of the plurality of metallization layers and the transistor gate layer.