Wafer-level package and methods of fabricating

• US 20010021541A1
• Filed: 04/09/2001
• Published: 09/13/2001
• Est. Priority Date: 06/28/1999
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Alan G. Wood, Salman Akram
• Inventors: Wood, Alan G., Akram, Salman
• Granted Patent: US 7,256,069 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention. Such a chip-scale package includes a semiconductor device invertedly disposed over the carrier such that bond pads of the semiconductor device substantially align with apertures formed through the carrier. Thus, the bond pads of the semiconductor device may communicate with the conductive bumps by means of the conductive material disposed in the apertures of the carrier. Methods of fabricating the carrier of the present invention and methods of fabricating chip-scale packages including the carrier are also within the scope of the present invention.

Claims

1. A method for fabricating a chip-scale package, comprising:

positioning a preformed polymeric film over a semiconductor device with at least one aperture that extends substantially longitudinally through said preformed polymeric film aligned with a corresponding bond pad of said semiconductor device; and

introducing conductive material into said at least one aperture.

2. The method of

claim 1

, further comprising adhering said preformed polymeric film to said semiconductor device.

3. The method of

claim 1

, further comprising defining said at least one aperture through said preformed polymeric film.

4. The method of

claim 3

, wherein said defining is effected after said positioning.

5. The method of

claim 7

, wherein said defining is effected before said positioning.

6. The method of

claim 1

, wherein said introducing comprises bonding said conductive material to said corresponding bond pad.

7. The method of

claim 1

, wherein said introducing comprises depositing said conductive material onto said preformed polymeric film and within said at least one aperture.

8. The method of

claim 7

, wherein said depositing comprises chemical vapor depositing or physical vapor depositing said conductive material.

9. The method of

claim 1

, wherein said introducing comprises placing a preformed conductive structure within said at least one aperture.

10. The method of

claim 1

, wherein said introducing is effected before said positioning.

11. The method of

claim 1

, wherein said introducing is effected after said positioning.

12. The method of

claim 1

, further comprising forming at least one contact at an end of said conductive material, opposite said semiconductor device.

13. The method of

claim 12

, further comprising placing a conductive structure adjacent said at least one contact.

14. The method of

claim 13

, wherein said placing comprises applying solder to said at least one contact.

15. The method of

claim 1

, further comprising positioning at least one conductive trace on said preformed polymeric film and in communication with said conductive material.

16. The method of

claim 15

, further comprising forming at least one contact in communication with said conductive trace.

17. The method of

claim 16

, further comprising placing a conductive structure adjacent said at least one contact.

18. The method of

claim 17

, wherein said placing comprises applying solder to said at least one contact.

19. The method of

claim 1

, further comprising placing said preformed polymeric film on at least a portion of a peripheral edge of said semiconductor device.

20. The method of

claim 17

, further comprising placing polymeric material at least laterally adjacent said at least one conductive structure.

21. The method of

claim 17

, further comprising placing a conductive elastomer over at least one conductive structure.

22. The method of

claim 21

, further comprising placing conductive structure in contact with said conductive elastomer, opposite said at least one conductive structure.

23. A method for fabricating a chip-scale package, comprising:

placing photoimageable polymeric material on a surface of a semiconductor device;

forming a polymeric film from said photoimageable polymeric material with at least one aperture extending substantially longitudinally through said polymeric film, said at least one aperture aligned with a corresponding bond pad of said semiconductor device; and

introducing conductive material into said at least one aperture.

24. The method of

claim 23

, wherein said forming comprises selectively exposing regions of said photoimageable polymeric material to electromagnetic radiation.

25. The method of

claim 23

, further comprising defining said at least one aperture through said polymeric film.

26. The method of

claim 25

, wherein said defining is effected after said forming.

27. The method of

claim 25

, wherein said defining is effected substantially simultaneously with said forming.

28. The method of

claim 23

, further comprising placing at least one conductive trace on said polymeric film and in communication with said conductive material.

29. The method of

claim 28

, further comprising placing at least one contact in communication with said at least one conductive trace.

30. The method of

claim 29

, further comprising placing at least one conductive structure adjacent said at least one contact.

31. The method of

claim 30

, further comprising placing polymeric material at least laterally adjacent said at least one conductive structure.

32. The method of

claim 30

, further comprising placing a conductive elastomer over said at least one conductive structure.

33. The method of

claim 32

, further comprising placing at least one other conductive structure in contact with said conductive elastomer, opposite said at least one conductive structure.

34. The method of

claim 23

, wherein said forming comprises forming said polymeric film so as to extend at least partially over a peripheral edge of said semiconductor device.