Low order channel flow control for an interleaved multiblock resource
First Claim
1. In a multiprocessor computer system defining two or more channels for transporting packets among system components during system cycles, a flow control system for preventing overflow of a system component configured to process at least two classes of packets, the flow control system comprising:
- a counter incremented in response to a packet of any class being issued to the interleaved component; and
flow control logic configured to suspend issuance of packets corresponding to a first class to the component in response to the counter reaching a predefined threshold.
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Abstract
A flow control technique prevents overflow of a write storage structure, such as a first-in, first-out (FIFO) queue, in a centralized Duplicate Tag store arrangement of a multiprocessor system that includes a plurality of nodes interconnected by a central switch. Each node comprises a plurality of processors with associated caches and memories interconnected by a local switch. Each node further comprises a Duplicate Tag (DTAG) store that contains information about the state of data relative to all processors of a node. The DTAG comprises the write FIFO which has a limited number of entries. Flow control logic in the local switch keeps track of when those entries may be occupied to avoid overflowing the FIFO.
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Citations
19 Claims
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1. In a multiprocessor computer system defining two or more channels for transporting packets among system components during system cycles, a flow control system for preventing overflow of a system component configured to process at least two classes of packets, the flow control system comprising:
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a counter incremented in response to a packet of any class being issued to the interleaved component; and
flow control logic configured to suspend issuance of packets corresponding to a first class to the component in response to the counter reaching a predefined threshold. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. In a multiprocessor computer system configured to issue request and response packets during system cycles, a flow control method for preventing overflow of a shared component having a limited number of resources, the flow control method comprising the steps of:
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providing a decrement ok (dec_ok) counter;
providing a write pending (wrt_pend) counter;
providing a last response flag;
providing a component busy signal that is moveable between an asserted and a dasserted condition;
incrementing the dec_ok counter and the wrt_pend counter in response to issuance of a request packet;
moving the component busy signal to the asserted condition during a given cycle in which a request or a response packet is issued;
asserting the last response flag during the cycle immediately following a given cycle in which a response packet is issued; and
suspending issuance of request packets when the wrt_pend counter exceeds a predetermined threshold, but continuing issuance of response packets. - View Dependent Claims (15, 16, 17, 18)
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19. A computer system comprising:
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a plurality of processors having private caches, the processors organized into quad building blocks (QBBs) and configured to cause the issuance by the system of packets across two or more channels;
a main memory subsystem disposed at each QBB, each main memory subsystem configured into a plurality of interleaved memory banks having addressable memory blocks;
a duplicate tag store (DTAG) disposed at each QBB, each DTAG having a DTAG array having a plurality of DTAG blocks for storing coherency information associated with the memory blocks buffered at the private caches of the QBB, each DTAG block associated with two or more interleaved memory banks;
a write first-in-first-out (FIFO) queue associated with each DTAG block configured to buffer coherency information to be loaded into the respective DTAG block;
a flow control system for preventing overflow of the write FIFO queues, the flow control system having a flow control engine associated with each DTAG block, each flow control engine comprising;
a decrement ok (dec_ok) counter;
a write pending (wrt_pend) counter;
a last response flag; and
a component busy signal that is moveable between an asserted and a deasserted condition, wherein in response to issuance of a packet on a first channel to the respective DTAG block, the dec_ok counter and the wrt_pend counters are both incremented, in response to issuance of a packet on either the first channel or a second channel to the respective DTAG block during a given cycle, the component busy signal is moved to the asserted condition during the given cycle, in response to issuance of a packet on the second channel to the respective DTAG block during a given cycle, the last response flag is asserted during the cycle immediately following the given cycle in which the second channel packet was issued, and when the wrt_pend counter exceeds a predetermined threshold, issuance of further packets on the first channel to the write FIFO queue of the respective DTAG block are suspended, but issuance of packets on the second channel to the write FIFO queue continues.
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Specification