Low order channel flow control for an interleaved multiblock resource

• US 20010049742A1
• Filed: 05/29/2001
• Published: 12/06/2001
• Est. Priority Date: 05/31/2000
• Status: Abandoned Application

• Current Assignee: Compaq Computer Corporation (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Nagpal, Hari Krishan, Steely, Simon C. Jr., Van Doren, Stephen R.
• Application Number:
  US09/867,111
• Publication Number:
  US 20010049742A1
• Time in Patent Office: Days
• US Class Current: 709/232
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

A flow control technique prevents overflow of a write storage structure, such as a first-in, first-out (FIFO) queue, in a centralized Duplicate Tag store arrangement of a multiprocessor system that includes a plurality of nodes interconnected by a central switch. Each node comprises a plurality of processors with associated caches and memories interconnected by a local switch. Each node further comprises a Duplicate Tag (DTAG) store that contains information about the state of data relative to all processors of a node. The DTAG comprises the write FIFO which has a limited number of entries. Flow control logic in the local switch keeps track of when those entries may be occupied to avoid overflowing the FIFO.

Claims

1. In a multiprocessor computer system defining two or more channels for transporting packets among system components during system cycles, a flow control system for preventing overflow of a system component configured to process at least two classes of packets, the flow control system comprising:

a counter incremented in response to a packet of any class being issued to the interleaved component; and

flow control logic configured to suspend issuance of packets corresponding to a first class to the component in response to the counter reaching a predefined threshold.

2. The flow control system of

claim 1

wherein the packet classes are hierarchically ordered between a highest class and a lowest class.

3. The flow control system of

claim 2

wherein packets corresponding to the lowest class are suspended upon the counter reaching the predefined threshold, while packets corresponding to the remaining higher classes continue to be issued to the component.

4. The flow control system of

claim 3

further comprising:

a last response flag; and

a component busy signal that is moveable between an asserted and a deasserted condition, wherein

in response to issuance of a packet of any class to the component during a given cycle, the component busy signal is moved to the asserted condition during the given cycle,

in response to issuance of a packet corresponding to a second class to the component during a given cycle, the last response flag is asserted during the cycle immediately following the given cycle in which the packet of the second class was issued, and

in response to both the last response flag and the component busy signal being deasserted, the counter is decremented.

5. The flow control system of

claim 4

further comprising a second counter incremented a predefined number of cycles following the issuance of each packet corresponding to the first class.

6. The flow control system of

claim 5

wherein the second counter is incremented by 1 and the first counter is incremented by 2.

7. The flow control system of

claim 6

wherein when the first counter drops below the predetermined threshold, issuance of packets corresponding to the first class resumes.

8. The flow control system of

claim 7

wherein packets corresponding to the first class are suspended provided that the second counter is greater than 0.

9. The flow control system of

claim 8

wherein the component is a write first-in-first-out (FIFO) queue of an interleaved duplicate cache tag store (DTAG), the write FIFO queue having a fixed number of entries for storing cache coherency information to be written to the DTAG.

10. The flow control system of

claim 9

wherein the write FIFO queue comprises a plurality of content addressable memory (CAM) units, each CAM unit having a plurality of cells for storing the cache coherency information.

11. The flow control system of

claim 10

further comprising a plurality of flow control engines, each flow control engine comprising:

a decrement ok (dec_ok) counter;

a write pending (wrt_pend) counter;

a last response flag; and

a component busy signal that is moveable between an asserted and a deasserted condition, wherein the multiprocessor computer system includes a plurality of DTAGs, and

each flow control engine associated with and configured to control the issuance of packets corresponding to the first class directed to a respective DTAG.

12. The flow control system of

claim 11

wherein the first class has a lower priority than the second class.

13. The flow control system of

claim 12

wherein the first class corresponds to request packets and the second class corresponds to response packets.

14. In a multiprocessor computer system configured to issue request and response packets during system cycles, a flow control method for preventing overflow of a shared component having a limited number of resources, the flow control method comprising the steps of:

providing a decrement ok (dec_ok) counter;

providing a write pending (wrt_pend) counter;

providing a last response flag;

providing a component busy signal that is moveable between an asserted and a dasserted condition;

incrementing the dec_ok counter and the wrt_pend counter in response to issuance of a request packet;

moving the component busy signal to the asserted condition during a given cycle in which a request or a response packet is issued;

asserting the last response flag during the cycle immediately following a given cycle in which a response packet is issued; and

suspending issuance of request packets when the wrt_pend counter exceeds a predetermined threshold, but continuing issuance of response packets.

15. The method of

claim 14

further comprising the step of decrementing the dec_ok and wrt_pend counters when both the last response flag and the component busy signal are deasserted.

16. The method of

claim 15

further comprising the step of further incrementing the dec_ok counter a predefined number of cycles following the issuance of a given request packet.

17. The method of

claim 16

further comprising the step of resuming issuance of request packets when the wrt_pend counter drops below the predetermined threshold.

18. The method of

claim 17

wherein

the dec_ok counter is incremented by 1,

the wrt_pend counter is incremented by 2, and

the step of suspending request packets further requires that the dec_ok counter be greater than 0.

19. A computer system comprising:

a plurality of processors having private caches, the processors organized into quad building blocks (QBBs) and configured to cause the issuance by the system of packets across two or more channels;

a main memory subsystem disposed at each QBB, each main memory subsystem configured into a plurality of interleaved memory banks having addressable memory blocks;

a duplicate tag store (DTAG) disposed at each QBB, each DTAG having a DTAG array having a plurality of DTAG blocks for storing coherency information associated with the memory blocks buffered at the private caches of the QBB, each DTAG block associated with two or more interleaved memory banks;

a write first-in-first-out (FIFO) queue associated with each DTAG block configured to buffer coherency information to be loaded into the respective DTAG block;

a flow control system for preventing overflow of the write FIFO queues, the flow control system having a flow control engine associated with each DTAG block, each flow control engine comprising;

a decrement ok (dec_ok) counter;

a write pending (wrt_pend) counter;

a last response flag; and

a component busy signal that is moveable between an asserted and a deasserted condition, wherein

in response to issuance of a packet on a first channel to the respective DTAG block, the dec_ok counter and the wrt_pend counters are both incremented,

in response to issuance of a packet on either the first channel or a second channel to the respective DTAG block during a given cycle, the component busy signal is moved to the asserted condition during the given cycle,

in response to issuance of a packet on the second channel to the respective DTAG block during a given cycle, the last response flag is asserted during the cycle immediately following the given cycle in which the second channel packet was issued, and

when the wrt_pend counter exceeds a predetermined threshold, issuance of further packets on the first channel to the write FIFO queue of the respective DTAG block are suspended, but issuance of packets on the second channel to the write FIFO queue continues.