Data storewidth accelerator

• US 20010052038A1
• Filed: 02/02/2001
• Published: 12/13/2001
• Est. Priority Date: 02/03/2000
• Status: Active Grant

• Current Assignee: Realtime Data LLC (Realtime Data Compression Systems, Inc.)
• Original Assignee: Realtime Data LLC (Realtime Data Compression Systems, Inc.)
• Inventors: Wolf-Sonkin, Yury, Fallon, James J.
• Granted Patent: US 6,748,457 B2
• Time in Patent Office: Days
• US Class Current: 710/68
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0676 Magnetic disk device
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/4408 Boot device selection
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Abstract

Data storage controllers employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one aspect, a data storage controller comprises a digital signal processor (DSP) comprising a data compression engine (DCE) for compressing data stored to the data storage device and for decompressing data retrieved from the data storage device; a programmable logic device, wherein the programmable logic device is programmed by the digital signal processor to instantiate a first interface for operatively interfacing the data storage controller to the data storage device and to instantiate a second interface for operatively interfacing the data storage controller to a host; and a non-volatile memory device, for storing logic code associated with the DSP, the first interface and the second interface. The data storage controller further comprises a cache memory device for temporarily storing data that is processed by or transmitted through the data storage controller. The data storage controller may comprise and expansion bus card that operatively attached to a host system bus. The data storage controller may be embedded within a motherboard of the host system.

Claims

1. A data storage controller for controlling storage and retrieval of data to and from a data storage device, the data storage controller comprising:

a digital signal processor (DSP) comprising a data compression engine (DCE) for compressing data stored to the data storage device and for decompressing data retrieved from the data storage device;

a programmable logic device, wherein the programmable logic device is programmed by the digital signal processor to (i) instantiate a first interface for operatively interfacing the data storage controller to the data storage device and to (ii) instantiate a second interface for operatively interfacing the data storage controller to a host; and

a non-volatile memory device, for storing logic code associated with the DSP, the first interface and the second interface.

2. The data storage controller of

claim 1

, further comprising a cache memory device for temporarily storing data that is processed by or transmitted through the data storage controller.

3. The data storage controller of

claim 2

, further comprising a DMA (direct memory access) controller that controls access of the cache memory device by the DCE, the first interface and the second interface.

4. The data storage controller of

claim 3

, wherein the DMA controller is implemented by one of the programmable logic device, the DSP and both.

5. The data storage controller of

claim 2

, wherein the DSP further comprises a bandwidth allocation controller for controlling access to the cache memory device by the DCE, the first interface and the second interface.

6. The data storage controller of

claim 4

, wherein the bandwidth allocation controller allocates bandwidth access to the cache memory device based on one of an anticipated and actual compression ratio of the DCE.

7. The data storage controller of

claim 1

, wherein the DSP comprises Input/Output ports for transmitting data from the data storage to a remote location and for receiving data transmitted from a remote location.

8. The data storage controller of

claim 7

, wherein the transmitted data comprises one of compressed data, uncompressed data and a combination thereof.

9. The data storage controller of

claim 1

, wherein the DSP comprises Input/Output ports that are dynamically reconfigured for programming the programmable logic device during initialization of the data storage controller.

10. The data storage controller of

claim 1

, wherein the DSP comprises a dedicated bus, operatively connected to the programmable logic device, for programming programmable logic device during initialization of the data storage controller.

11. The data storage controller of

claim 1

, wherein the data storage controller comprises an expansion bus card that operatively connects to a host system bus.

12. The data storage controller of

claim 1

, wherein the data storage controller is embedded within a host system motherboard.

13. The data storage controller of

claim 1

, wherein the DSP is configured to sense the host system environment upon initialization of the data storage controller and select a first and second interface logic in the non-volatile memory that corresponds to the host system environment.

14. The data storage controller of

claim 1

, wherein the DSP programs the programmable logic device in advance of initialization of the host system.

15. The data storage controller of

claim 1

, wherein the data storage controller comprises a boot configuration circuit that generates a control signal that causes the DSP to program the programmable logic device in advance of initialization of the host system.

16. The data storage controller of

claim 1

, wherein the first interface comprises a RAID (redundant array of independent disks)interface.

17. The data storage controller of

claim 1

, wherein the data storage controller comprises a boot device controller.

18. The data storage controller of

claim 17

, wherein the data storage controller is programmed to preload boot data into local memory of the data storage controller prior commencement of a boot process of the host system, wherein the data storage controller services requests by the host system for the boot data from the local memory.

19. The data storage controller of

claim 1

, wherein the DCE implements a content independent data compression system.