Semiconductor integrated circuit

• US 20020080663A1
• Filed: 12/21/2001
• Published: 06/27/2002
• Est. Priority Date: 12/26/2000
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohuchi, Kazunori, Ohuchi, Sachiko, Fuse, Tsuneaki, Yoshida, Masako, Kameyama, Atsushi
• Granted Patent: US 6,677,797 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

An integrate circuit has a first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a pMISFET circuit block and an nMISFET circuit block each with a high threshold value, while the second logic circuit has a pMISFET circuit block and an nMISFET circuit block each with a low threshold value. An output switch circuit intervenes between the pMISFET and nMISFET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.

Claims

1. A semiconductor integrated circuit comprising:

a first logic circuit which has a first input terminal and comprises a logic block that essentially connects a first pMIS logic block made up of a pMISFET with a threshold voltage of Vtp1 and a first nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn1 in series between a first power supply with a potential of V1 and a reference potential;

a second logic circuit which has a second input terminal connected to said first input terminal and which has the same logic function as that of said first logic circuit and comprises a logic block that essentially connects a second pMIS logic block made up of a pMISFET with a threshold voltage of Vtp2 (Vtp2<

Vtp1) and a second nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn2 (Vtn2<

Vtn1) in series between a second power supply with a potential of V2 (V2<

V1) and said reference potential; and

an output switch circuit which intervenes between said first pMIS logic block and said first nMIS inverted-logic block in said first logic circuit and between said second pMIS logic block and said second nMIS inverted-logic block in said second logic circuit, and which has a control signal terminal to which a control signal is inputted and an output terminal that switches between an output of said first logic circuit and an output of said second logic circuit according to said control signal.

2. The semiconductor integrated circuit according to claim 1, wherein said output switch circuit sets one of said first logic circuit and said second logic circuit to a low impedance and the other to a high impedance and outputs said output of said one of said first logic circuit and said second logic circuit set to said low impedance to said output terminal.

3. The semiconductor integrated circuit according to claim 1, wherein said output switch circuit includes

a first switch circuit comprising a first pMISFET and a first nMISFET connected in series between said first pMIS logic block and said first nMIS inverted-logic block in said first logic circuit, and

a second switch circuit comprising a second pMISFET and a second nMISFET connected in series between said second pMIS logic block and said second nMIS inverted-logic block in said second logic circuit, a connection node of said first pMISFET and said first nMISFET and a connection node of said second pMISFET and said second nMISFET being connected to said output terminal, and

when said first pMISFET and said first nMISFET are on according to said control signal, said second pMISFET and said second nMISFET are off, and when said first pMISFET and said first nMISFET are off, said second pMISFEET and said second nMISFET are on.

4. The semiconductor integrated circuit according to claim 3, wherein said control signal to switch said output is inputted to gates of said first pMISFET of said first logic circuit and said second nMISFET of said second logic circuit and an inverted signal of said control signal is inputted to gates of said first nMISFET of said first logic circuit and said second pMISFET of said second logic circuit.

5. The semiconductor integrated circuit according to claim 1, wherein said output switch circuit comprises a first switch circuit where a first pMISFET and a first nMISFET are connected in series between said first pMIS logic block and said first nMIS inverted-logic block in said first logic circuit, a connection node of said first pMISFET and said first nMISFET being connected to said output terminal, and a second switch circuit where a second and a third nMISFET are connected in series between said second pMIS logic block and said second nMIS inverted-logic block in said second logic circuit, a connection node of said second and said third nMISFET being connected to said output terminal, and

when each of said MISFETs in one of said first switch circuit and said second switch circuit is on according to said control signal, each of said MISFETs in the other switch circuit is off.

6. The semiconductor integrated circuit according to claim 5, wherein said control signal is inputted to gates of said first pMISFET of said first switch circuit and said second and said third nMISFET of said second switch circuit and an inverted signal of said control signal is inputted to a gate of said first nMISFET of said first switch circuit.

7. The semiconductor integrated circuit according to claim 1, wherein each of said first and said second logic circuit functions as an inverter.

8. A semiconductor integrated circuit which uses a semiconductor integrated circuit of claim 7 as an inverter section of a flip-flop.

9. The semiconductor integrated circuit according to claim 8, wherein said second power supply is connected via a switching MIS transistor to said second logic circuit and, when said output switch circuit selects said output of said first logic circuit, said second logic circuit is disconnected from said second power supply.

10. The semiconductor integrated circuit according to claim 1, wherein each of said first and said second logic circuit is one selected from the group consisting of a NAND gate, a NOR gate and a combined gate configuration.

11. A semiconductor integrated circuit comprising:

a first switching gate to which an input signal is supplied;

a master flip-flop which includes a semiconductor integrated circuit of claim 1 and to which an input signal is inputted via said first switching gate;

a second switching gate to which an output signal of said master flip-flop is supplied;

a slave flip-flop which includes a semiconductor integrated circuit of claim 1 and to which said output signal of said master flip-flop is inputted via said second switching gate; and

a buffer circuit which includes a semiconductor integrated circuit of claim 1 and controls said first and said second switching gate.

13. The semiconductor integrated circuit according to claim 12, wherein said output switch circuit outputs a constant potential.

14. The semiconductor integrated circuit according to claim 12, wherein said output switch circuit switches one of said first logic circuit and said second logic circuit to a low impedance and the other to a high impedance and outputs said output of the logic circuit switched to said low impedance to said output terminal.

15. The semiconductor integrated circuit according to claim 12, wherein said output switch circuit includes

a first switching pMISFET and a first switching nMISFET connected in series between said first pMIS logic block and said first nMIS inverted-logic block in said first logic circuit, and

a second switching pMISFET and a second switching nMISFET connected in series between said second pMIS logic block and said second nMIS inverted-logic block in said second logic circuit, a connection node of said first pMISFET and said first nMISFET and a connection node of said second pMISFET and said second nMISFET being connected to said output terminal, and

when said first pMISFET and said first nMISFET are on according to said control signal, said second pMISFET and said second nMISFET are off, and when said first pMISFET and said first nMISFET are off, said second pMISFEET and said second nMISFET are on.

16. The semiconductor integrated circuit according to claim 15, wherein said control signal to switch the output is inputted to gates of said first pMISFET of said first logic circuit and said second nMISFET of said second logic circuit and an inverted signal of said control signal is inputted to gates of said first nMISFET of said first logic circuit and said second pMISFET of said second logic circuit.

17. The semiconductor integrated circuit according to claim 12, wherein said output switch circuit is composed of a first switch circuit where a first pMISFET and a first nMISFET are connected in series between said first pMIS logic block and said first nMIS inverted-logic block in said first logic circuit, a connection node of said first pMISFET and said first nMISFET being connected to said output terminal, and a second switch circuit where a second and a third nMISFET are connected in series between said second pMIS logic block and said second nMIS inverted-logic block in said second logic circuit, a connection node of said second and said third nMISFET being connected to said output terminal, and

when each of said MISFETs in one of said first switch circuit and said second switch circuit is on according to said control signal, each of said MISFETs in the other switch circuit is off.

18. The semiconductor integrated circuit according to claim 17, wherein said control signal is inputted to gates of said first pMISFET of said first switch circuit and said second and said third nMISFET of said second switch circuit and an inverted signal of said control signal is inputted to a gate of said first nMISFET of said first switch circuit.

12. A semiconductor integrated circuit comprising:

a first logic circuit which has a first input terminal and comprises a logic block that essentially connects a first pMIS logic block made up of a pMISFET with a threshold voltage of Vtp1 and a first nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn1 in series between a first power supply with a potential of V1 and a reference potential;

a second logic circuit with a second input terminal which has a different logic function from that of said first logic circuit and which comprises a logic block that essentially connects a second pMIS logic block made up of a pMISFET with a threshold voltage of Vtp2 (Vtp2<

Vtp1) and a second nMIS inverted-logic block made up of an nMISFET with a threshold voltage of Vtn2 (Vtn2<

Vtn1) in series between a second power supply with a potential of V2 (V2<

V1) and said reference potential; and

an output switch circuit which intervenes between said first pMIS logic block and said first nMIS inverted-logic block in said first logic circuit and between said second pMIS logic block and said second nMIS inverted-logic block in said second logic circuit, and which has a control signal terminal to which a control signal is inputted and an output terminal that switches between an output of said first logic circuit and an output of said second logic circuit according to said control signal.