Carrier with metal bumps for semiconductor die packages

• US 20020167075A1
• Filed: 05/14/2001
• Published: 11/14/2002
• Est. Priority Date: 05/14/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Madrid, Ruben
• Granted Patent: US 6,893,901 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4878 Mechanical treatment, e.g. deforming
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73153 Bump and layer connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.

Claims

1. A carrier for a semiconductor die package, the carrier comprising:

(a) a metal layer; and

(b) a plurality of bumps formed in the metal layer,

wherein the carrier is for electrically coupling a semiconductor die to a circuit substrate.

2. The carrier of claim 1 wherein the metal layer comprises copper.

3. The carrier of claim 1 wherein the plurality of bumps are disposed in an array and are stamped bumps.

4. The carrier of claim 1 further comprising:

a die attach region, and wherein the plurality of bumps are arranged around the die attach region.

5. The carrier of claim 1 further comprising a dielectric layer, wherein the metal layer is on a dielectric layer.

6. The carrier of claim 1 wherein the metal layer includes one or more sublayers of material on a base metal.

7. The carrier of claim 1 wherein the metal layer is discontinuous and includes a plurality of etched conductive lines that lead to the plurality of bumps.

8. The carrier of claim 1 wherein each bump has a conical angle of about 40 degrees of more.

9. The carrier of claim 1 wherein each bump has a conical shape.

10. A semiconductor die package comprising:

(a) a carrier comprising a metal layer, a die attach region, and a plurality of bumps formed in the metal layer; and

(b) a semiconductor die electrically coupled to the die attach region of the carrier.

11. The die package of claim 10 wherein the plurality of bumps are stamped bumps and are arranged around the die attach region, and wherein each of the bumps has a height that is greater than or equal to a thickness of the semiconductor die.

12. The die package of claim 10 wherein the carrier comprises copper.

13. The die package of claim 10 wherein the carrier comprises:

a base metal with one or more coatings on the base metal.

14. The die package of claim 10 wherein each bump has a conical angle greater than about 40 degrees.

15. The die package of claim 10 wherein the semiconductor die comprises a vertical metal oxide semiconductor field effect transistor (MOSFET) device.

16. The die package of claim 10 wherein the semiconductor die comprises a vertical metal oxide semiconductor field effect transistor (MOSFET) device having a source region, a gate region, and a drain region, wherein the drain region is proximate to the die attach region of the carrier, and the source region and the gate region are distal to the die attach region of the carrier.

17. The die package of claim 10 wherein each stamped bump has a conical shape.

18. The die package of claim 10 wherein the bumps and the semiconductor die are at opposite sides of the carrier.

19. The die package of claim 10 wherein the bumps and the semiconductor die are at the same side of the carrier.

20. A semiconductor die package comprising:

(a) a carrier comprising metal layer, a die attach region, and a plurality of stamped bumps formed in the metal layer around the die attach region;

(b) a semiconductor die comprising a vertical metal oxide semiconductor field effect transistor (MOSFET) device having a source region, a gate region, and a drain region, wherein the drain region is electrically coupled to and proximate to the die attach region of the carrier, and the source region and the gate region are distal to the die attach region, and wherein the plurality of stamped bumps in the carrier are arranged around the semiconductor die; and

(c) a plurality of solder deposits disposed on the semiconductor die.

21. The semiconductor die package of claim 20 wherein the each of the bumps has a conical angle greater than about 40 degrees or more.

22. The semiconductor die package of claim 20 wherein the carrier comprises copper.

23. The semiconductor die package of claim 20 the plurality of bumps are formed simultaneously in the metal layer.

25. The method of claim 24 wherein forming the plurality of bumps comprises stamping.

27. The method of claim 26 wherein (c) attaching comprises:

attaching the semiconductor die to a die attach region of the carrier, and wherein the plurality of bumps is disposed around the semiconductor die.

28. The method of claim 26 wherein forming the plurality of bumps comprises stamping.

24. A method for forming a carrier for a semiconductor die package, the method comprising:

(a) providing a metal layer; and

(b) forming a plurality of bumps in the metal layer, wherein the formed bumps are capable of being electrically coupled to conductive regions of a circuit substrate.

26. A method for forming a semiconductor die package, the method comprising:

(a) forming a carrier according to the method of claim 24; and

(b) attaching a semiconductor die to the metal layer after forming the plurality of bumps.