Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

• US 20030057416A1
• Filed: 09/20/2002
• Published: 03/27/2003
• Est. Priority Date: 09/21/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Hammond, Richard, Currie, Matthew, Lochtefeld, Anthony, Fitzgerald, Eugene
• Granted Patent: US 6,831,292 B2
• Time in Patent Office: Days
• US Class Current: 257/19
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Claims

1. A semiconductor structure comprising:

a substrate; and

at least one strained layer disposed on the substrate, thereby defining an interface therebetween, the at least one strained layer having a distal zone away from the interface;

wherein the substrate, the interface, and the at least one strained layer are characterized at least in part by an impurity gradient having a value substantially equal to zero in the distal zone.

2. The semiconductor structure of claim 1 wherein the substrate comprises Si.

3. The semiconductor structure of claim 1 wherein the substrate comprises SiGe.

4. The semiconductor structure of claim 1 wherein the substrate comprises a p-type dopant.

5. The semiconductor structure of claim 1 wherein the substrate comprises an n-type dopant.

6. The semiconductor structure of claim 1 wherein the substrate comprises a plurality of layers.

7. The semiconductor structure of claim 6 wherein the plurality of layers comprises relaxed SiGe disposed on compositionally graded SiGe.

8. The semiconductor structure of claim 6 wherein the plurality of layers comprises relaxed SiGe disposed on Si.

9. The semiconductor structure of claim 6 wherein the plurality of layers comprises a buried insulating layer.

10. The semiconductor structure of claim 1 wherein the at least one strained layer comprises Si.

11. The semiconductor structure of claim 1 wherein the at least one strained layer comprises Ge.

12. The semiconductor structure of claim 1 wherein the at least one strained layer comprises SiGe.

13. The semiconductor structure of claim 1 wherein the distal zone comprises at least about fifty Angstroms of the at least one strained layer.

14. The semiconductor structure of claim 10 wherein the impurity gradient describes at least the concentration of Ge.

15. The semiconductor structure of claim 11 wherein the impurity gradient describes at least the concentration of Si.

16. A FET fabricated in a semiconductor substrate, the FET comprising a channel region including at least one strained channel layer, the at least one strained channel layer having a distal zone away from the substrate, wherein the substrate and the channel region are characterized at least in part by an impurity gradient having a value substantially equal to zero in the distal zone.

17. The FET of claim 16 wherein the substrate comprises Si.

18. The FET of claim 16 wherein the substrate comprises SiGe.

19. The FET of claim 16 wherein the substrate comprises a p-type dopant.

20. The FET of claim 16 wherein the substrate comprises an n-type dopant.

21. The FET of claim 16 wherein the substrate comprises a plurality of layers.

22. The FET of claim 21 wherein the plurality of layers comprises relaxed SiGe disposed on compositionally graded SiGe.

23. The FET of claim 21 wherein the plurality of layers comprises relaxed SiGe disposed on Si.

24. The FET of claim 21 wherein the plurality of layers comprises a buried insulating layer.

25. The FET of claim 16 wherein the at least one strained channel layer comprises Si.

26. The FET of claim 16 wherein the at least one strained channel layer comprises Ge.

27. The FET of claim 16 wherein the at least one strained channel layer comprises SiGe.

28. The FET of claim 16 wherein the distal zone comprises at least about fifty Angstroms of the at least one strained channel layer.

29. The FET of claim 25 wherein the impurity gradient describes at least the concentration of Ge.

30. The FET of claim 26 wherein the impurity gradient describes at least the concentration of Si.

31. A method for fabricating a semiconductor structure in a substrate, the method comprising the steps of:

disposing at least one strained layer on the substrate thereby defining an interface therebetween, the at least one strained layer having a distal zone away from the interface; and

performing at least one subsequent processing step on the substrate after which an impurity gradient characterizing, at least in part, the substrate, the interface, and the at least one strained layer has a value substantially equal to zero in the distal zone.

32. The method of claim 31 wherein the substrate comprises Si.

33. The method of claim 31 wherein the substrate comprises SiGe.

34. The method of claim 31 wherein the substrate comprises a p-type dopant.

35. The method of claim 31 wherein the substrate comprises an n-type dopant.

36. The method of claim 31 wherein the substrate comprises a plurality of layers.

37. The method of claim 36 wherein the plurality of layers comprises relaxed SiGe disposed on compositionally graded SiGe.

38. The method of claim 36 wherein the plurality of layers comprises relaxed SiGe disposed on Si.

39. The method of claim 36 wherein the plurality of layers comprises a buried insulating layer.

40. The method of claim 31 wherein the at least one strained layer comprises Si.

41. The method of claim 31 wherein the at least one strained layer comprises Ge.

42. The method of claim 31 wherein the at least one strained layer comprises SiGe.

43. The method of claim 31 wherein the distal zone comprises at least about fifty Angstroms of the at least one strained layer.

44. The method of claim 31 wherein the at least one subsequent processing step is performed within a predetermined temperature range.

45. The method of claim 40 wherein the impurity gradient describes at least the concentration of Ge.

46. The method of claim 41 wherein the impurity gradient describes at least the concentration of Si.

47. A method for fabricating a FET in a semiconductor substrate, the FET comprising a channel region, the method comprising the steps of:

disposing at least one strained channel layer in at least the channel region, the at least one strained channel layer having a distal zone away from the substrate; and

performing at least one subsequent processing step on the substrate after which an impurity gradient characterizing, at least in part, the substrate and the at least one strained layer has a value substantially equal to zero in the distal zone.

48. The method of claim 47 wherein the substrate comprises Si.

49. The method of claim 47 wherein the substrate comprises SiGe.

50. The method of claim 47 wherein the substrate comprises a p-type dopant.

51. The method of claim 47 wherein the substrate comprises an p-type dopant.

52. The method of claim 47 wherein the substrate comprises a plurality of layers.

53. The method of claim 52 wherein the plurality of layers comprises relaxed SiGe disposed on compositionally graded SiGe.

54. The method of claim 52 wherein the plurality of layers comprises relaxed SiGe disposed on Si.

55. The method of claim 52 wherein the plurality of layers comprises a buried insulating layer.

56. The method of claim 47 wherein the at least one strained layer comprises Si.

57. The method of claim 47 wherein the at least one strained layer comprises Ge.

58. The method of claim 47 wherein the at least one strained layer comprises SiGe.

59. The method of claim 47 wherein the distal zone comprises at least about fifty Angstroms of the at least one strained layer.

60. The method of claim 47 wherein the at least one subsequent processing step is performed within a predetermined temperature range.

61. The method of claim 56 wherein the impurity gradient describes at least the concentration of Ge.

62. The method of claim 57 wherein the impurity gradient describes at least the concentration of Si.