CMOS image sensor system with self-reset digital pixel architecture for improving SNR and dynamic range
First Claim
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1. A self-reset digital pixel sensor (DPS), comprising:
- a diode capable of collecting more charge than physical well capacity of said DPS;
a feedback circuit capable of affecting at least one self-reset during a single integration whenever said diode reaches saturation;
a digitizing means capable of providing pixel level analog-to-digital conversion (ADC) converting analog pixel signal to digital pixel value;
a memory means coupled to said digitizing means for storing said digital pixel value; and
a comparing means coupled to said feedback circuit, said digitizing means, and said memory means for facilitating said at least one self-reset and said pixel level ADC.
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Abstract
A CMOS DPS image sensor architecture for improving SNR and dynamic range is presented. The CMOS DPS architecture includes self-reset digital pixels capable of collecting more charge than the physical well capacity. A method for improving SNR without reducing dynamic range in a CMOS video sensor system under low illumination is described, wherein the CMOS video sensor system employing self-reset DPS architecture includes pixel level A/D conversion and wherein each DPS pixels is capable of resetting itself whenever a corresponding diode reaches saturation during integration time.
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Citations
20 Claims
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1. A self-reset digital pixel sensor (DPS), comprising:
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a diode capable of collecting more charge than physical well capacity of said DPS;
a feedback circuit capable of affecting at least one self-reset during a single integration whenever said diode reaches saturation;
a digitizing means capable of providing pixel level analog-to-digital conversion (ADC) converting analog pixel signal to digital pixel value;
a memory means coupled to said digitizing means for storing said digital pixel value; and
a comparing means coupled to said feedback circuit, said digitizing means, and said memory means for facilitating said at least one self-reset and said pixel level ADC. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A self-reset digital pixel sensor (DPS) architecture with self-reset DPS for improving signal-to-noise ratio (SNR) and extending dynamic range, wherein said DPS architecture capable of capturing multiple pixel samples during a single integration, said architecture comprising:
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a diode capable of collecting more charge than physical well capacity of said DPS;
a feedback circuit capable of affecting at least one self-reset during said integration whenever said diode reaches saturation;
a digitizing means capable of providing multiple pixel level analog-to-digital conversions (ADCs) for converting analog pixel signals to corresponding digital pixel values during said integration;
a memory means coupled to said digitizing means for storing said digital pixel values; and
a comparing means coupled to said feedback circuit, said digitizing means, and said memory means for facilitating said at least one self-reset and said ADCs. - View Dependent Claims (11, 12, 13, 14)
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15. A complementary metal oxide semiconductor (CMOS) image sensor system with self-reset digital pixel sensor (DPS) architecture for improving signal-to-noise ratio (SNR) and extending dynamic range, wherein said DPS architecture capable of capturing multiple pixel samples during a single integration, said CMOS image sensor system comprising:
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at least one self-reset DPS pixel, said DPS pixel comprising;
a diode capable of collecting more charge than physical well capacity of said DPS;
a feedback circuit capable of providing at least one self-reset during said integration whenever said diode reaches saturation;
a digitizing means capable of providing multiple pixel level analog-to-digital conversions (ADCs) for converting analog pixel signals to corresponding digital pixel values during said integration;
a memory means coupled to said digitizing means for storing said digital pixel values; and
a comparing means coupled to said feedback circuit, said digitizing means, and said memory means for facilitating said at least one self-reset and said ADCs; and
a counting means for determining number of self-reset occurred during said integration by analyzing number of pixel samples captured during said integration. - View Dependent Claims (16, 19)
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- 17. The CMOS image sensor system 15, wherein peak SNR of said DPS is not limited by said physical well capacity.
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20. A method for simultaneously improving dynamic range and signal-to-noise (SNR) in a complementary metal oxide semiconductor (CMOS) image sensing system employing self-reset digital pixel sensor (DPS) architecture, wherein said self-reset DPS capable of resetting itself whenever said DPS reaches saturation during a single integration and wherein said self-reset DPS capable of collecting more charge than physical well capacity of said DPS, the method comprising the steps of:
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capturing multiple pixel samples during said integration;
converting at pixel level captured analog pixel sample signals to corresponding digital pixel values;
storing said digital pixel values in memory;
obtaining at high speed said digital pixel values from said memory;
determining number of self-reset occurred during said integration by analyzing said digital pixel values;
determining total charge collected during said integration by analyzing said number of self-reset;
performing linear mean-square-error estimation to reduce noise associated with said capturing step thereby extending said dynamic range at low illumination end and increasing said SNR.
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Specification