Three-dimensional memory
First Claim
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1. A three-dimensional integrated memory (3DiM), comprising:
- a substrate circuit, said substrate circuit further comprising a substrate integrated circuit and a first address-decoder, said substrate integrated circuit comprising an embedded RWM and/or an embedded processor;
a three-dimensional memory (3D-M), at least a memory level in said 3D-M being stacked on top of said substrate circuit, said memory level being connected with said substrate circuit through a plurality of inter-level connecting vias and/or contact vias.
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Abstract
One greatest advantage of the three-dimensional memory (3D-M) is its integratibility. In a three-dimensional integrated memory (3DiM), the 3D-M is integrated with an embedded RWM and/or an embedded processor. Collectively, the 3DiM excels in speed, density/cost, programmability and data security. The present invention makes further improvements to three-dimensional mask-programmable read-only memory. Another 3D-M application of great importance is in the area of IC-testing. The 3D-M carrying test vectors can be integrated with the circuit-under-test, thus supporting field self-test and at-speed test.
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Citations
32 Claims
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1. A three-dimensional integrated memory (3DiM), comprising:
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a substrate circuit, said substrate circuit further comprising a substrate integrated circuit and a first address-decoder, said substrate integrated circuit comprising an embedded RWM and/or an embedded processor;
a three-dimensional memory (3D-M), at least a memory level in said 3D-M being stacked on top of said substrate circuit, said memory level being connected with said substrate circuit through a plurality of inter-level connecting vias and/or contact vias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A read-only memory, comprising:
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at least a first address-selection line with a first width;
at least a second address-selection line with a second width;
at least a 3D-ROM cell, said 3D-ROM cell comprising a top electrode, a bottom electrode and a 3D-ROM layer between said top and bottom electrodes, said top electrode being connected with said first address-selection line, said bottom electrode being connected with said second address-selection line, said 3D-ROM layer comprising a quasi-conduction layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A three-dimensional memory (3D-M), comprising
a substrate circuit, said substrate circuit comprising a peripheral circuit, said peripheral circuit further comprising a data sense-amplifier; -
a memory level stacked on said substrate circuit, said memory level comprising a unit array, said unit array further comprising a data bit line;
said data bit line being connected with said data sense-amplifier through an inter-level connecting via and/or a contact via. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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- 28. An integrated circuit supporting three-dimensional-memory-based self-test (3DMST), comprising a circuit-under-test and a three-dimensional memory (3D-M) integrated thereon, at least a portion of said 3D-M storing at least a portion of test data and/or test-data seeds for said circuit-under-test.
Specification