Three-dimensional memory

• US 20030067043A1
• Filed: 08/28/2002
• Published: 04/10/2003
• Est. Priority Date: 10/07/2001
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Granted Patent: US 6,717,222 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 29/822 for read only memories
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors

Abstract

One greatest advantage of the three-dimensional memory (3D-M) is its integratibility. In a three-dimensional integrated memory (3DiM), the 3D-M is integrated with an embedded RWM and/or an embedded processor. Collectively, the 3DiM excels in speed, density/cost, programmability and data security. The present invention makes further improvements to three-dimensional mask-programmable read-only memory. Another 3D-M application of great importance is in the area of IC-testing. The 3D-M carrying test vectors can be integrated with the circuit-under-test, thus supporting field self-test and at-speed test.

Claims

1. A three-dimensional integrated memory (3DiM), comprising:

a substrate circuit, said substrate circuit further comprising a substrate integrated circuit and a first address-decoder, said substrate integrated circuit comprising an embedded RWM and/or an embedded processor;

a three-dimensional memory (3D-M), at least a memory level in said 3D-M being stacked on top of said substrate circuit, said memory level being connected with said substrate circuit through a plurality of inter-level connecting vias and/or contact vias.

2. The 3DiM according to claim 1, wherein said memory level comprises poly-crystalline semiconductor material, and the interconnect system of said substrate circuit is made of refractory conductor and thermally-stable dielectric.

3. The 3DiM according to claim 1, further comprising an address-translation block, a second address-decoder and a unified memory space formed by at least a portion of said embedded RWM and at least a portion of said 3D-M, said second address-decoder decoding the address for said unified memory space, at least a portion of the output of said address-translation block being eventually connected with at least a portion of the input of said second address-decoder.

4. The 3DiM according to claim 1, further comprising a data-processing block selected from a group consisting of D/A converter, decoder and decryption engine.

5. The 3DiM according to claim 1, further comprising a shielding layer between said substrate circuit and at least a portion of said memory level.

6. The 3DiM according to claim 1, further comprising:

at least an interconnect gap between two adjacent address-selection lines on said memory level,

at least an embedded wire, said embedded wire passing through said memory level in said interconnect gap.

7. The 3DiM according to claim 1, further comprising at least a routing level in the interconnect system of said substrate circuit, said routing level providing electrical connection between said memory level and said first address-decoder.

8. The 3DiM according to claim 1, wherein said embedded RWM comprises an embedded RAM, at least a portion of the input/output of said embedded RAM being eventually connected with at least a portion of the input/output of said first address decoder, whereby said embedded RAM stores a copy of the 3D-M data.

9. The 3DiM according to claim 1, wherein

said embedded RWM comprises an embedded ROM, whereby said embedded ROM stores correctional data and/or upgrade codes for said memory level;

and

said substrate circuit further comprises means for selecting data from said memory level or from said embedded ROM.

10. A read-only memory, comprising:

at least a first address-selection line with a first width;

at least a second address-selection line with a second width;

at least a 3D-ROM cell, said 3D-ROM cell comprising a top electrode, a bottom electrode and a 3D-ROM layer between said top and bottom electrodes, said top electrode being connected with said first address-selection line, said bottom electrode being connected with said second address-selection line, said 3D-ROM layer comprising a quasi-conduction layer.

11. The read-only memory according to claim 10 being a mask-programmable read-only memory, wherein said 3D-ROM cell further comprises an info-opening, whose dimension along said first address-selection line is larger than said second width.

12. The read-only memory according to claim 10 being a three-dimensional mask-programmable read-only memory and further comprising a first memory level and a second memory level, said first memory level being stacked on top of said second memory level and sharing at least one address-selection line with said second memory level.

13. The read-only memory according to claim 10 being a mask-programmable read-only memory, wherein one dimension of said 3D-ROM layer is equal to said first width;

and the other dimension of said 3D-ROM layer is equal to said second width.

14. The read-only memory according to claim 10 being a mask-programmable read-only memory, wherein said 3D-ROM layer is a natural junction located at the intersection of said first and second address-selection lines, a first and second portions of said natural junction being located in said first and second address-selection lines, respectively.

15. The read-only memory according to claim 10 being a mask-programmable read-only memory, wherein at least one address-selection line is made of semiconductor material.

16. The read-only memory according to claim 10 being a mask-programmable read-only memory, wherein at least one address-selection line comprises a semiconductor material, said semiconductor material further comprising at least a metal element introduced by metal-ion implant.

17. The read-only memory according to claim 10, wherein said 3D-ROM layer is a polarized layer and/or has a polarized structure.

18. The read-only memory according to claim 10, wherein said 3D-ROM cell is a seamless 3D-ROM cell or a quasi-seamless 3D-ROM cell.

19. The read-only memory according to claim 10, wherein said 3D-ROM cell comprises a high-bandgap semiconductor and/or micro-crystalline semiconductor material.

20. A three-dimensional memory (3D-M), comprising

a substrate circuit, said substrate circuit comprising a peripheral circuit, said peripheral circuit further comprising a data sense-amplifier;

a memory level stacked on said substrate circuit, said memory level comprising a unit array, said unit array further comprising a data bit line;

said data bit line being connected with said data sense-amplifier through an inter-level connecting via and/or a contact via.

21. The 3D-M according to claim 20, wherein all bit lines in said unit array are connected to a constant dc-source through a group of switches, said group of switches being controlled by one control signal.

22. The 3D-M according to claim 20, further comprising at least a bit line selected from a group consisting of a first timing bit line, a second timing bit and a dummy bit line, whereby the signal from said first timing bit line starts the data sampling for said data sense-amplifier;

the signal from said second timing bit line ends the data sampling for said data sense-amplifier;

said dummy bit line is connected with one input of said data sense-amplifier.

23. The 3D-M according to claim 20, further comprising a state-control signal, which controls the connection between all address-selection lines in said unit array and a constant dc-source.

24. The 3D-M according to claim 20, wherein said unit array comprises a first and second memory cells, said first memory cell being connected to a first sub-decoder, said second memory cell being connected to a second sub-decoder, said first and second sub-decoders sharing an input address.

25. The 3D-M according to claim 20, wherein the number of bit lines in said unit array is larger than the number of word lines in said unit array.

26. The 3D-M according to claim 20, wherein said substrate circuit further comprises a read-voltage generating block and/or a programming-voltage input pad, whereby said read-voltage generating block supplies a read voltage larger than the supply voltage to said unit array, said programming-voltage input pad feeds an external programming voltage to said unit array.

27. The 3D-M according to claim 20, further comprising:

a composite line, said composite line including a highly-conductive layer and a lightly-doped layer at the bottom of said composite line;

a via and an inverted-U link, said via being connected with said composite line by said inverted-U link through contacts to said highly-conductive layer on top and/or on sidewall.

28. An integrated circuit supporting three-dimensional-memory-based self-test (3DMST), comprising a circuit-under-test and a three-dimensional memory (3D-M) integrated thereon, at least a portion of said 3D-M storing at least a portion of test data and/or test-data seeds for said circuit-under-test.

29. The integrated circuit according to claim 28, wherein said test data or test-data seeds are downloaded into said circuit-under-test in a serial and/or parallel fashion.

30. The integrated circuit according to claim 28, further supporting at least one testing type selected from parallel self-test, mixed-signal testing and printed-circuit board system self-test.

31. The integrated circuit according to claim 28, further supporting test-data compression and/or composite test.

32. The integrated circuit according to claim 28, wherein the testing methodology for said integrated circuit is 3DMST-with-confidence and/or dual testing.