Antifuse structure and method of making
First Claim
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1. An antifuse structure comprising an antifuse between first and second thermal conduction regions, wherein:
- each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity; and
the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse.
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Accused Products
Abstract
An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.
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Citations
53 Claims
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1. An antifuse structure comprising an antifuse between first and second thermal conduction regions, wherein:
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each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity; and
the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory structure comprising:
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a column line between top and bottom row lines;
top and bottom antifuses respectively between;
the bottom row line and the column line; and
the column line and the top row line;
wherein;
each of the top and bottom antifuses is between top and bottom thermal conduction regions;
each of the top and bottom thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity;
each said portion of high thermal conductivity is selected from the group consisting of the column line and the first and second row lines; and
each said portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the respective antifuse. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A memory structure comprising:
a memory cell including;
a row line;
an antifuse layer in electrical communication with the row line through an interface;
a control element in electrical communication with the antifuse layer; and
a column line in electrical communication with the control element;
a dielectric region interfacing the memory cell;
wherein the antifuse layer is thermally isolated from the row line and the column line. - View Dependent Claims (18, 19, 20)
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21. A memory structure comprising:
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a memory cell including;
a row line;
an electrical insulator having an electrical contact therein;
an electrode in electrical communication with the row line through the electrical contact;
an antifuse layer in electrical communication with the electrode;
a control element in electrical communication with the antifuse layer; and
a column line in electrical communication with the control element;
a dielectric region interfacing the memory cell. - View Dependent Claims (22, 23, 24)
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25. A memory structure comprising:
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a first row line;
a column line;
a first antifuse layer;
a first control element; and
a dielectric region interfacing each of the column line, the first antifuse layer, and the first control element;
wherein;
the row line is in electrical communication with the first antifuse layer through an interface; and
the first antifuse layer is in electrical communication with the first control element;
wherein the antifuse layer is thermally isolated from the row line and the column line. - View Dependent Claims (26, 27, 28)
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29. A memory structure comprising:
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a first and second row lines each interfacing, respectively, first and second dielectric regions;
a column line;
first and second antifuse layers;
first and second control elements; and
a third dielectric region interfacing each of the column line, the first and second antifuse layers, and the first and second control elements;
wherein;
the row line is in electrical communication with the first antifuse layer through a thermal and electrical interface;
the first antifuse layer is in electrical communication with the first control element;
the first control element is in electrical communication with the column line;
the column line is in electrical communication with the second antifuse layer through a thermal and electrical interface;
the second antifuse layer is in electrical communication with the second control element; and
the second control element is in electrical communication with the second row line. - View Dependent Claims (30)
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31. A one time programmable memory device, comprising:
a memory structure including, an antifuse structure having an antifuse between first and second thermal conduction regions;
each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity; and
the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse. - View Dependent Claims (32, 33)
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34. A method comprising:
forming an antifuse between first and second thermal conduction regions, wherein;
each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high conductivity; and
the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse. - View Dependent Claims (35, 37, 38, 39)
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40. A method of making a memory structure, the method comprising:
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forming a bottom row line;
forming a bottom antifuse above the bottom row line with a thermal interface there between;
forming a bottom control element about the bottom antifuse;
forming a column line over the bottom control element;
forming a top antifuse over the column line with a thermal interface there between;
forming a top control element over the top antifuse; and
forming a top row line over the top control element. - View Dependent Claims (41, 42)
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43. A method of making a memory structure, the method comprising:
forming a memory cell over a substrate by;
forming a patterned row line over the substrate;
forming an electrical insulator upon the patterned row and having a plurality of via plugs therein that is in electrical communication with the patterned row line;
forming a first electrode upon the electrical insulator and the via plugs therein;
forming a plurality of patterned stacks upon the first electrode each including an antifuse layer and a control element;
forming a dielectric fill upon the first electrode and interfacing the plurality of patterned stacks;
forming a second electrode upon the patterned stacks and the dielectric fill;
forming a second electrical insulator upon the second electrode and having a plurality of via plugs therein; and
forming a patterned column line upon the second electrical insulator and the via plugs therein. - View Dependent Claims (44, 45, 46)
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47. A method of making a memory structure, the method comprising:
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forming a first electrical insulator upon a first patterned row, the first electrical insulator having a plurality of via plugs therein that are in electrical communication with the first patterned row line;
forming a first electrode upon the first electrical insulator and the via plugs therein;
forming a plurality of first patterned stacks upon the first electrode each including an antifuse layer and a control element;
forming a first dielectric fill upon the first electrode and interfacing the plurality of first patterned stacks;
forming a second electrode upon the first patterned stacks;
forming a second electrical insulator upon the second electrode, the second electrical insulator having a plurality of via plugs therein; and
forming a patterned column line in electrical communication with the via plugs in the second electrical insulator;
forming a third electrical insulator upon the patterned column line and having a plurality of via plugs therein that are in electrical communication with the patterned column line;
forming a third electrode upon the third electrical insulator and the plurality of via plugs therein;
forming a plurality of second patterned stacks upon the third electrode each including an antifuse layer and a control element;
forming a second dielectric fill upon the third electrode and interfacing the plurality of second patterned stacks;
forming a fourth electrode upon the second dielectric fill;
forming a fourth electrical insulator upon the fourth electrode, the fourth electrical insulator having a plurality of via plugs therein that are in electrical communication with the fourth electrode; and
forming a second patterned row line over the fourth electrical insulator and in electrical communication with the via plug in the fourth electrical insulator. - View Dependent Claims (48, 49)
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50. A memory structure comprising a plurality of means for storing data;
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each said means for storing data includes means, between first and second thermal conduction regions, for programming the means for storing data; and
each of the first and second thermal conduction regions has;
a means for providing a low thermal conductivity; and
a means for providing a high thermal conductivity;
wherein the means for providing a low thermal conductivity is between the respective said means for providing a high thermal conductivity and the means for programming the means for storing data. - View Dependent Claims (51, 52, 53)
- wherein;
Specification