Antifuse structure and method of making

• US 20030173592A1
• Filed: 03/12/2003
• Published: 09/18/2003
• Est. Priority Date: 01/16/2002
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Brocklin, Andrew L.Van, Fricke, Peter
• Granted Patent: US 6,677,220 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.

Claims

1. An antifuse structure comprising an antifuse between first and second thermal conduction regions, wherein:

each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity; and

the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse.

2. The antifuse structure as defined in claim 1, wherein the portion having low thermal conductivity has a thermal conductivity less by about an order of magnitude than that of the portion of high thermal conductivity.

3. The antifuse structure as defined in claim 1, wherein:

each said portion having high thermal conductivity includes an electrically conductive line;

the portion having low thermal conductivity of the first thermal conduction region includes a first electrode;

the portion having low thermal conductivity of the second first thermal conduction region includes;

a second electrode; and

a control element interfacing the second electrode and being selected from the group consisting of diode and a tunnel junction.

4. The antifuse structure as defined in claim 1, wherein:

each said portion having high thermal conductivity includes an electrically conductive line;

the portion having low thermal conductivity of the first thermal conduction region includes a first electrode;

the portion having low thermal conductivity of the second thermal conduction region includes;

a second and third electrodes; and

a control element interfacing both the second and third electrodes and being selected from the group consisting of diode and a tunnel junction.

5. The antifuse structure as defined in claim 1, wherein:

each said portion having high thermal conductivity includes an electrically conductive line;

the portion having low thermal conductivity of the first thermal conduction region includes first and second electrodes;

the portion having low thermal conductivity of the second first thermal conduction region includes;

a third and fourth electrodes; and

a control element interfacing both the third and fourth electrodes and being selected from the group consisting of diode and a tunnel junction.

6. The antifuse structure as defined in claim 1, wherein the portion having high thermal conductivity includes an electrically conductive line.

7. The antifuse structure as defined in claim 6, wherein:

the antifuse is within an antifuse layer that includes first and second electrical conductors;

each of the first and second thermal conduction regions includes a thermal insulator having a plurality of via plugs therein;

the first thermal conduction region interfaces the first electrical conductor; and

the second thermal conduction region interfaces the second electrical conductor.

8. The antifuse structure as defined in claim 7, wherein:

the antifuse layer is within a memory structure in which the first electrical conductor is a row line and the second electrical conductor is a column line;

the first thermal conduction region includes an electrode;

the second thermal conduction region includes an electrode;

a control element is between the antifuse layer and the second thermal conduction region, wherein;

the control element interfaces the antifuse layer and is selected from the group consisting of diode and a tunnel junction; and

the antifuse layer interfaces the electrode of the second thermal conduction region.

9. The antifuse structure as defined in claim 7, wherein:

the antifuse layer is within a memory structure in which the first electrical conductor is a row line and the second electrical conductor is a column line;

the first thermal conduction region includes a first electrode;

the second thermal conduction region includes second and third electrodes;

a control element is between the second and third electrodes, wherein;

the second thermal conduction region interfaces the antifuse layer;

the control element interfaces the third electrode and is selected from the group consisting of diode and a tunnel junction; and

the third electrode interfaces the antifuse layer.

10. The antifuse structure as defined in claim 7, wherein:

the antifuse layer is within a memory structure in which the first electrical conductor is a row line and the second electrical conductor is a column line;

the antifuse layer is sandwiched between first and second electrodes;

the first thermal conduction region includes;

the first electrode; and

a third electrode;

the second thermal conduction region includes;

the second electrode; and

a fourth electrode;

a control element is between the second and fourth electrodes, wherein;

the control element is selected from the group consisting of diode and a tunnel junction;

the second thermal conduction region interfaces the antifuse layer; and

the first electrode interfaces the third electrode.

11. A memory structure comprising:

a column line between top and bottom row lines;

top and bottom antifuses respectively between;

the bottom row line and the column line; and

the column line and the top row line;

wherein;

each of the top and bottom antifuses is between top and bottom thermal conduction regions;

each of the top and bottom thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity;

each said portion of high thermal conductivity is selected from the group consisting of the column line and the first and second row lines; and

each said portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the respective antifuse.

12. The memory structure as defined in claim 11, wherein each said portion having low thermal conductivity has a thermal conductivity less by about an order of magnitude than that of each said portion of high thermal conductivity.

13. The memory structure as defined in claim 11, wherein:

each said portion having low thermal conductivity of the top thermal conduction region includes a first electrode;

each said portion having low thermal conductivity of the bottom thermal conduction region further includes;

a second electrode; and

a control element interfacing the second electrode and being selected from the group consisting of diode and a tunnel junction.

14. The memory structure as defined in claim 11, wherein:

the portion having low thermal conductivity of the top thermal conduction region includes a first electrode;

the portion having low thermal conductivity of the bottom thermal conduction region further includes;

second and third electrodes; and

a control element interfacing both the second and third electrodes and being selected from the group consisting of diode and a tunnel junction.

15. The memory structure as defined in claim 11, wherein:

the portion having low thermal conductivity of the top thermal conduction region includes first and second electrodes;

the portion having low thermal conductivity of the bottom thermal conduction region further includes;

third and fourth electrodes; and

a control element interfacing both the third and fourth electrodes and being selected from the group consisting of diode and a tunnel junction.

16. The memory structure as defined in claim 11, wherein:

each said antifuse is within an antifuse layer; and

each said portion of low thermal conductivity includes a thermal insulator having a plurality of via plugs therein

17. A memory structure comprising:

a memory cell including;

a row line;

an antifuse layer in electrical communication with the row line through an interface;

a control element in electrical communication with the antifuse layer; and

a column line in electrical communication with the control element;

a dielectric region interfacing the memory cell;

wherein the antifuse layer is thermally isolated from the row line and the column line.

18. The memory structure as defined in claim 17, further comprising a plurality of the memory cells, vertically offset one from another by the dielectric region.

19. The memory structure as defined in claim 17, wherein:

the row line and the column line each comprise aluminum or an alloy thereof;

the interface to the antifuse layer from the row line comprises a refractory metal or alloy thereof;

the dielectric region comprises silicon dioxide; and

at least a portion of the control element comprises lightly doped amorphous or microcrystalline silicon.

20. The memory structure as defined in claim 17, wherein the control element is selected from the group consisting of a diode and a tunnel junction.

21. A memory structure comprising:

a memory cell including;

a row line;

an electrical insulator having an electrical contact therein;

an electrode in electrical communication with the row line through the electrical contact;

an antifuse layer in electrical communication with the electrode;

a control element in electrical communication with the antifuse layer; and

a column line in electrical communication with the control element;

a dielectric region interfacing the memory cell.

22. The memory structure as defined in claim 21, further comprising a plurality of the memory cells electrically insulated one from another by the dielectric region.

23. The memory structure as defined in claim 21, wherein:

the row line and the column line each comprise aluminum or an alloy thereof;

the electrical contact comprises a refractory metal or alloy thereof;

the dielectric region comprises silicon dioxide;

at least a portion of the control element comprises lightly doped amorphous or microcrystalline silicon; and

the antifuse layer comprises alumina.

24. The memory structure as defined in claim 21, wherein the control element is a diode or a tunnel junction.

25. A memory structure comprising:

a first row line;

a column line;

a first antifuse layer;

a first control element; and

a dielectric region interfacing each of the column line, the first antifuse layer, and the first control element;

wherein;

the row line is in electrical communication with the first antifuse layer through an interface; and

the first antifuse layer is in electrical communication with the first control element;

wherein the antifuse layer is thermally isolated from the row line and the column line.

26. The memory structure as defined in claim 25, further comprising:

a second row line;

a second antifuse layer; and

a second control element;

wherein;

the dielectric region interfaces each of the second antifuse layer and the second control element;

the column line is in electrical communication with the second antifuse layer through an interface;

the second antifuse layer is in electrical communication with the second control element;

the second control element is in electrical communication with the second row line.

27. The memory structure as defined in claim 26, wherein:

the first and second row lines and the column line each comprise aluminum or an alloy thereof;

the respective interface from the row line and column line to the first and second antifuse layers each comprises a refractory metal or alloy thereof;

the first, second and third dielectric regions each comprise silicon dioxide;

at least a portion of the first and second control elements comprises lightly doped amorphous or microcrystalline silicon; and

the first and second antifuse layers each comprise alumina.

28. The memory structure as defined in claim 26, wherein the first and second control elements are each selected from the group consisting of a diode and a tunnel junction.

29. A memory structure comprising:

a first and second row lines each interfacing, respectively, first and second dielectric regions;

a column line;

first and second antifuse layers;

first and second control elements; and

a third dielectric region interfacing each of the column line, the first and second antifuse layers, and the first and second control elements;

wherein;

the row line is in electrical communication with the first antifuse layer through a thermal and electrical interface;

the first antifuse layer is in electrical communication with the first control element;

the first control element is in electrical communication with the column line;

the column line is in electrical communication with the second antifuse layer through a thermal and electrical interface;

the second antifuse layer is in electrical communication with the second control element; and

the second control element is in electrical communication with the second row line.

30. The memory structure as defined in claim 29, wherein:

the first and second row lines and the column line each comprise aluminum or an alloy thereof;

the respective interface from the row line and column line to the first and second antifuse layers each comprises a refractory metal or alloy thereof;

the first, second and third dielectric regions each comprise silicon dioxide;

at least a portion of the first and second control elements comprises lightly doped amorphous or microcrystalline silicon;

the first and second antifuse layers each comprise alumina; and

the first and second control elements are each selected from the group consisting of a diode and a tunnel junction.

31. A one time programmable memory device, comprising:

a memory structure including,

an antifuse structure having an antifuse between first and second thermal conduction regions;

each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity; and

the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse.

32. A digital film for use in a digital camera, comprising at least one memory device of claim 31.

33. A memory card for permanent or removable memory media use in an electronic apparatus selected from the group consisting of a computing device, a multifunction peripheral, a cellular telephone, a personal digital assistant, a facsimile machine, a desk top scanner, a high volume copier, a music playing device, a video playing device, and a portable or fixed electronic apparatus, comprising the memory device of claim 31.

34. A method comprising:

forming an antifuse between first and second thermal conduction regions, wherein;

each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high conductivity; and

the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse.

35. The method as defined in claim 34, wherein the portion having low thermal conductivity has a thermal conductivity less by about an order of magnitude than that of the portion of high thermal conductivity.

37. A memory structure comprising an antifuse structure made by the method of claim 34.

38. A memory device selected from the group consisting of a WORM memory device and a one time programmable memory device, comprising the memory structure as defined in claim 37.

39. A memory apparatus that is selected from the group consisting of a digital film and a memory card, comprising the memory device as defined in claim 38.

40. A method of making a memory structure, the method comprising:

forming a bottom row line;

forming a bottom antifuse above the bottom row line with a thermal interface there between;

forming a bottom control element about the bottom antifuse;

forming a column line over the bottom control element;

forming a top antifuse over the column line with a thermal interface there between;

forming a top control element over the top antifuse; and

forming a top row line over the top control element.

41. The method as defined in claim 40, wherein:

each of the top and bottom antifuses is between top and bottom thermal conduction regions;

each of the top and bottom thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity;

each said portion of high thermal conductivity is selected from the group consisting of the column line and the bottom and top row lines; and

each said portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the respective one of the top and bottom antifuses.

42. The method as defined in claim 41, wherein each said portion having low thermal conductivity has a thermal conductivity less by about an order of magnitude than that of each said portion of high thermal conductivity.

43. A method of making a memory structure, the method comprising:

forming a memory cell over a substrate by;

forming a patterned row line over the substrate;

forming an electrical insulator upon the patterned row and having a plurality of via plugs therein that is in electrical communication with the patterned row line;

forming a first electrode upon the electrical insulator and the via plugs therein;

forming a plurality of patterned stacks upon the first electrode each including an antifuse layer and a control element;

forming a dielectric fill upon the first electrode and interfacing the plurality of patterned stacks;

forming a second electrode upon the patterned stacks and the dielectric fill;

forming a second electrical insulator upon the second electrode and having a plurality of via plugs therein; and

forming a patterned column line upon the second electrical insulator and the via plugs therein.

44. The method as defined in claim 43, further comprising forming a plurality of said memory cell each being vertically offset one from another by an interlayer dielectric.

45. The method as defined in claim 43, wherein:

the row line and the column line each comprise aluminum or an alloy thereof;

the via plugs each comprise refractory metal or alloy thereof;

the dielectric fill comprises silicon dioxide;

at least a portion of the control element comprises lightly doped amorphous or microcrystalline silicon; and

the antifuse layer comprises alumina.

46. The method as defined in claim 43, wherein the control element is selected from the group consisting of a diode and a tunnel junction.

47. A method of making a memory structure, the method comprising:

forming a first electrical insulator upon a first patterned row, the first electrical insulator having a plurality of via plugs therein that are in electrical communication with the first patterned row line;

forming a first electrode upon the first electrical insulator and the via plugs therein;

forming a plurality of first patterned stacks upon the first electrode each including an antifuse layer and a control element;

forming a first dielectric fill upon the first electrode and interfacing the plurality of first patterned stacks;

forming a second electrode upon the first patterned stacks;

forming a second electrical insulator upon the second electrode, the second electrical insulator having a plurality of via plugs therein; and

forming a patterned column line in electrical communication with the via plugs in the second electrical insulator;

forming a third electrical insulator upon the patterned column line and having a plurality of via plugs therein that are in electrical communication with the patterned column line;

forming a third electrode upon the third electrical insulator and the plurality of via plugs therein;

forming a plurality of second patterned stacks upon the third electrode each including an antifuse layer and a control element;

forming a second dielectric fill upon the third electrode and interfacing the plurality of second patterned stacks;

forming a fourth electrode upon the second dielectric fill;

forming a fourth electrical insulator upon the fourth electrode, the fourth electrical insulator having a plurality of via plugs therein that are in electrical communication with the fourth electrode; and

forming a second patterned row line over the fourth electrical insulator and in electrical communication with the via plug in the fourth electrical insulator.

48. The method as defined in claim 47, wherein:

the first and second row lines and the column line each comprise aluminum or an alloy thereof;

the via plugs each comprises a refractory metal or alloy thereof;

the first and second dielectric fills each comprise silicon dioxide;

at least a portion of each said control element comprises lightly doped amorphous or microcrystalline silicon;

the first and second antifuse layers each comprise alumina.

49. The method as defined in claim 47, wherein each said control element is selected from the group consisting of a diode and a tunnel junction.

50. A memory structure comprising a plurality of means for storing data;

wherein;

each said means for storing data includes means, between first and second thermal conduction regions, for programming the means for storing data; and

each of the first and second thermal conduction regions has;

a means for providing a low thermal conductivity; and

a means for providing a high thermal conductivity;

wherein the means for providing a low thermal conductivity is between the respective said means for providing a high thermal conductivity and the means for programming the means for storing data.

51. The memory structure as defined in claim 50, wherein the means for providing a low thermal conductivity has a thermal conductivity less by about an order of magnitude than that of the means for providing a high thermal conductivity.

52. The memory structure as defined in claim 50, wherein:

the means for programming the means for storing data comprises a voltage breakdown element;

each said means for providing a high thermal conductivity includes an electrically conductive line;

the means for providing a low thermal conductivity of the first thermal conduction region includes a first electrode;

the means for providing a low thermal conductivity of the second first thermal conduction region includes;

a second electrode; and

a control element interfacing the second electrode and being selected from the group consisting of diode and a tunnel junction.

53. The memory structure as defined in claim 52, wherein the voltage breakdown element comprises an antifuse.