Memory system

• US 20030202383A1
• Filed: 04/02/2003
• Published: 10/30/2003
• Est. Priority Date: 02/07/2002
• Status: Active Grant

• Current Assignee: Emergence Memory Solutions LLC
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Nakamura, Yasuhiro, Hara, Fumio, Shiota, Shigemasa, Goto, Hiroyuki, Shibuya, Hirofumi
• Granted Patent: US 6,882,568 B2
• Time in Patent Office: Days
• US Class Current: 365/185.33
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Claims

1. A memory system comprising:

a rewritable nonvolatile memory;

a buffer memory; and

a controller,

wherein said controller controls, in response to an access request from an external apparatus, first data transfer between said controller and said external apparatus, second data transfer between said controller and said nonvolatile memory, and third data transfer between said controller and said buffer memory, controls transfer from said controller to said buffer memory and transfer from said buffer memory to said controller in said third data transfer in a time sharing manner, and enables said first data transfer or said second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

2. The memory system according to claim 1, wherein operation speed of said third data transfer is about twice as high as data transfer speed of said first data transfer.

3. The memory system according to claim 2, wherein the buffer memory is a single-port clock-synchronous volatile memory and operates in an FIFO manner.

4. The memory system according to claim 3, wherein said controller comprises a dual-port data buffer disposed between said external apparatus and the buffer memory and a dual-port data buffer disposed between said buffer memory and said nonvolatile memory.

5. The memory system according to claim 4, wherein a nonvolatile memory is a flash memory.

6. A memory system comprising:

a rewritable nonvolatile memory;

a buffer memory; and

a controller,

said controller including;

a first data transfer control unit connected to an external apparatus;

a second data transfer control unit connected to said nonvolatile memory; and

a transfer arbitrator which is connected to said buffer memory and controls data transfer to/from the buffer memory in response to a transfer request from said first data transfer control unit and a transfer request from said second data transfer control unit,

wherein said first data transfer control unit is connected to the external apparatus and the transfer arbitrator via a data buffer and outputs a transfer request to the transfer arbitrator,

wherein said second data transfer control unit is connected to the nonvolatile memory and the transfer arbitrator via a data buffer and outputs a transfer request to the transfer arbitrator, and

wherein the transfer arbitrator controls transfer of write data to said buffer memory and transfer of read data from said buffer memory in a time sharing manner in response to a transfer request from said first data transfer control unit and a transfer request from said second data transfer control unit.

7. The memory system according to claim 6, wherein said data buffer has dual ports.

8. The memory system according to claim 6, wherein in response to a write access request from the outside, said first data transfer control unit outputs a transfer request for writing data to the buffer memory to the transfer arbitrator when a predetermined amount of data is stored in the data buffer from the external apparatus, and said second data transfer control unit outputs a transfer request for reading data from the buffer memory to the data buffer to the transfer arbitrator when data in the data buffer is less than the predetermined amount.

9. The memory system according to claim 6, wherein in response to a read access request from the outside, said second data transfer control unit outputs a transfer request for writing data to the buffer memory to the transfer arbitrator when a predetermined amount of data is stored in the data buffer from the buffer memory, and said first data transfer control unit outputs a transfer request for reading data from the buffer memory to the transfer arbitrator when data in the data buffer is less than the predetermined amount.

10. The memory system according to claim 6, wherein operation speed of the data transfer to/from the buffer memory by said transfer arbitrator is about twice as high as operation speed of data transfer to/from the outside by said first transfer control unit.

11. The memory system according to claim 9, wherein the buffer memory is a single-port clock-synchronous DRAM and operates in an FIFO manner.

12. The memory system according to claim 10, wherein the nonvolatile memory is a flash memory.

13. A nonvolatile memory system comprising:

a controller;

a buffer memory;

a nonvolatile memory;

a first signal line connected to the controller, for transferring data to/from the outside;

a second signal line connecting the controller to the buffer memory; and

a third signal line connecting the controller to the nonvolatile memory,

wherein a data transfer rate of said second signal line is equal to or higher than a sum of a data transfer rate of said first signal line and a data transfer rate of said third signal line.

14. The nonvolatile memory system according to claim 13, wherein the data transfer rate of said first signal line is equal to or higher than the data transfer rate of said third signal line.

15. The nonvolatile memory system according to claim 14, wherein a clock signal line is included in said second signal line, and said buffer memory is a memory to/from which data is input/output synchronously with a clock signal.

16. The nonvolatile memory system according to claim 15, wherein in the case of storing data supplied from the outside into said nonvolatile memory, in said second signal line, transfer of data which is supplied from the outside and temporarily stored in the buffer memory and transfer of data which is temporarily stored in the buffer memory and is stored into said nonvolatile memory are performed in a time sharing manner.

17. The nonvolatile memory system according to claim 15, wherein in the case of supplying data stored in said nonvolatile memory to the outside, in said second signal line, transfer of data which is read from said nonvolatile memory and temporarily stored in the buffer memory and transfer of data which is temporarily stored in the buffer memory and is supplied to the outside are performed in a time sharing manner.

18. The nonvolatile memory system according to claim 13, further comprising a plurality of said nonvolatile memories, and a data transfer rate of said third signal line is equal to a sum of data transfer rates of said plurality of nonvolatile memories.

19. The nonvolatile memory system according to claim 18, wherein the data transfer rate of said first signal line is equal to or higher than the data transfer rate of said third signal line.

20. The nonvolatile memory system according to claim 19, wherein a clock signal is included in said second signal line, and said buffer memory is a memory to/from which data is input/output synchronously with a clock.

21. The nonvolatile memory system according to claim 20, wherein in the case of storing data supplied from the outside into said nonvolatile memory, in said second signal line, transfer of data which is supplied from the outside and temporarily stored into the buffer memory and transfer of data which is temporarily stored in the buffer memory and stored into any of said plurality of nonvolatile memories are performed in a time sharing manner.

22. The nonvolatile memory system according to claim 20, wherein in the case of supplying data stored in said nonvolatile memory to the outside, in said second signal line, transfer of data which is read from any of said plurality of nonvolatile memories and temporarily stored into the buffer memory and transfer of data which is temporarily stored in the buffer memory and supplied to the outside are performed in a time sharing manner.