Memory system
First Claim
1. A memory system comprising:
- a rewritable nonvolatile memory;
a buffer memory; and
a controller, wherein said controller controls, in response to an access request from an external apparatus, first data transfer between said controller and said external apparatus, second data transfer between said controller and said nonvolatile memory, and third data transfer between said controller and said buffer memory, controls transfer from said controller to said buffer memory and transfer from said buffer memory to said controller in said third data transfer in a time sharing manner, and enables said first data transfer or said second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
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Accused Products
Abstract
The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
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Citations
22 Claims
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1. A memory system comprising:
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a rewritable nonvolatile memory;
a buffer memory; and
a controller, wherein said controller controls, in response to an access request from an external apparatus, first data transfer between said controller and said external apparatus, second data transfer between said controller and said nonvolatile memory, and third data transfer between said controller and said buffer memory, controls transfer from said controller to said buffer memory and transfer from said buffer memory to said controller in said third data transfer in a time sharing manner, and enables said first data transfer or said second data transfer to be performed in parallel with the transfer carried out in the time sharing manner. - View Dependent Claims (2, 3, 4, 5)
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6. A memory system comprising:
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a rewritable nonvolatile memory;
a buffer memory; and
a controller, said controller including;
a first data transfer control unit connected to an external apparatus;
a second data transfer control unit connected to said nonvolatile memory; and
a transfer arbitrator which is connected to said buffer memory and controls data transfer to/from the buffer memory in response to a transfer request from said first data transfer control unit and a transfer request from said second data transfer control unit, wherein said first data transfer control unit is connected to the external apparatus and the transfer arbitrator via a data buffer and outputs a transfer request to the transfer arbitrator, wherein said second data transfer control unit is connected to the nonvolatile memory and the transfer arbitrator via a data buffer and outputs a transfer request to the transfer arbitrator, and wherein the transfer arbitrator controls transfer of write data to said buffer memory and transfer of read data from said buffer memory in a time sharing manner in response to a transfer request from said first data transfer control unit and a transfer request from said second data transfer control unit. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A nonvolatile memory system comprising:
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a controller;
a buffer memory;
a nonvolatile memory;
a first signal line connected to the controller, for transferring data to/from the outside;
a second signal line connecting the controller to the buffer memory; and
a third signal line connecting the controller to the nonvolatile memory, wherein a data transfer rate of said second signal line is equal to or higher than a sum of a data transfer rate of said first signal line and a data transfer rate of said third signal line. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification