Pixel cell with high storage capacitance for a CMOS imager
First Claim
Patent Images
1. A source follower transistor for use in a CMOS imaging device, said transistor comprising:
- a source region formed in a substrate;
a drain region formed in the substrate;
a gate layer formed on the substrate between said source region and said drain region, wherein said gate has an active area of from about 0.3 μ
m2 to about 25 μ
m2, and wherein said gate layer is adapted to be electrically connected to receive charge from a photocharge collector.
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Abstract
A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 μm2 to about 10 μm2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.
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Citations
94 Claims
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1. A source follower transistor for use in a CMOS imaging device, said transistor comprising:
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a source region formed in a substrate;
a drain region formed in the substrate;
a gate layer formed on the substrate between said source region and said drain region, wherein said gate has an active area of from about 0.3 μ
m2 to about 25 μ
m2, and wherein said gate layer is adapted to be electrically connected to receive charge from a photocharge collector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A pixel sensor cell for use in a CMOS imaging device, said cell comprising:
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a doped layer formed in a substrate;
a photocharge collector formed on at least a portion of said doped layer for controlling image charge accumulation in said doped layer; and
a source follower transistor having a gate for receiving charge collected by said photocharge collector and for providing a signal representing image charge, wherein the gate of said source follower transistor has an active area of from about 0.3 μ
m2 to about 25 μ
m2. - View Dependent Claims (12, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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14. The pixel sensor cell of claim 14, wherein the first conductivity type is p-type.
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31. A pixel sensor cell for use in a CMOS imaging device, said cell comprising:
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a doped layer formed in a substrate;
a photocharge collector formed on at least a portion of said doped layer for controlling image charge accumulation in said doped layer;
a doped region formed in said doped layer adjacent to said photocharge collector for receiving image charge transferred from said doped layer; and
a source follower transistor having a gate electrically connected to receive charge from said doped region and for providing a signal representing image charge transferred to said doped region, wherein the gate of said source follower transistor has an active area of from about 0.3 μ
m2 to about 25 μ
m2. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. A CMOS imager comprising:
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a doped layer formed in a substrate, an array of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has a photocharge collector and a source follower transistor having a gate, the gate of the source follower transistor receiving charge collected by said photocharge collector and having an active area of from about 0.3 μ
m2 to about 25 μ
m2; and
signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image. - View Dependent Claims (51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
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62. An array of pixel sensor cells comprising:
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a doped layer formed in a substrate;
a plurality of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has a source follower transistor having a gate having an active area of from about 0.3 μ
m2 to about 25 μ
m2. - View Dependent Claims (63, 64, 65, 66, 67)
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68. An imaging system for generating output signals based on an image focused on the imaging system, comprising:
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a plurality of pixel cells arranged into an array of rows and columns, each pixel cell being operable to generate a voltage at a diffusion node corresponding to detected light intensity by the cell, wherein each pixel cell has a source follower transistor with a gate having an active area of from about 0.3 μ
m2 to about 25 μ
m2;
a row decoder having a plurality of control lines connected to the cell array, each control line being connected to the cells in a respective row, wherein the row decoder is operable to activate the cells in a row; and
a plurality of output circuits each including a respective output transistor, each output circuit being connected to a respective cell of said array, each circuit being operable to store voltage signals received from a respective cell and to provide a cell output signal. - View Dependent Claims (69, 70, 71, 72)
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73. An integrated circuit imager comprising:
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a CMOS imager, said CMOS imager comprising an array of pixel sensor cells formed in a doped layer on a substrate, wherein each pixel sensor cell has a source follower transistor having an active area of from about 1.0 μ
m2 to about 15.0 μ
m2, and signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and
a processor for receiving and processing data representing said image.
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74. A method of forming a source follower transistor for use in a CMOS imaging device, said method comprising the steps of:
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forming a doped layer in a substrate;
forming a first doped region and a second doped region in the doped layer;
forming an insulating layer on the doped layer between the first and the second doped regions;
forming a gate layer on the insulating layer, wherein the gate layer having an active area of from about 0.3 μ
m2 to about 25 μ
m2, and wherein the gate layer is adapted to be electrically connected to receive charge from a photocharge collector. - View Dependent Claims (75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87)
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88. A method of forming a pixel cell for use in a CMOS imaging device, said method comprising the steps of:
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forming a doped layer in a substrate;
forming a photocharge collector on said doped layer; and
forming a source follower transistor having a gate on said doped layer, wherein the gate having an active area of from about 0.3 μ
m2 to about 25 μ
m2. - View Dependent Claims (89, 90, 91, 92, 93, 94)
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Specification