Self-aligned body tie for a partially depleted SOI device structure
First Claim
1. A self-aligned body tie for a partially depleted silicon-on-insulator device structure, comprising in combination:
- an active region on a silicon-on-insulator substrate;
an N-channel device and a P-channel device formed on the active region;
a first body tie providing a conduction path from a p-well region of the N-channel device to a P+ body contact; and
a second body tie providing a conduction path from an n-well region of a P-channel device to an N+ body contact.
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Accused Products
Abstract
A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.
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Citations
63 Claims
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1. A self-aligned body tie for a partially depleted silicon-on-insulator device structure, comprising in combination:
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an active region on a silicon-on-insulator substrate;
an N-channel device and a P-channel device formed on the active region;
a first body tie providing a conduction path from a p-well region of the N-channel device to a P+ body contact; and
a second body tie providing a conduction path from an n-well region of a P-channel device to an N+ body contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A self-aligned body tie for a partially depleted silicon-on-insulator device structure, comprising in combination:
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an active region on a silicon-on-insulator substrate;
an N-channel device and a P-channel device formed on the active region, wherein the N-channel device includes an N+ drain, an N+ source, and a gate, wherein the P-channel device includes a P+ drain, a P+ source, and the gate, and wherein the gate extends onto a surrounding field oxide layer to provide interconnection between transistors and contacts;
a first body tie providing a conduction path from a p-well region of the N-channel device to a P+ body contact, wherein the P+ body contact is located substantially adjacent to the N+ source;
a second body tie providing a conduction path from an n-well region of a P-channel device to an N+ body contact, wherein the N+ body contact is located substantially adjacent to the P+ source; and
wherein gate spacers are located substantially adjacent to both sides of the p-well region and the n-well region, wherein the N+ drain and the N+ source are located substantially adjacent to the gate spacers on opposite sides of the p-well region, wherein the P+ drain and the P+ source are located substantially adjacent to the gate spacers on opposite sides of the n-well region, wherein body tie spacers are located substantially adjacent to the P+ body contact and the N+ body contact, and wherein the first body tie and the second body tie are located substantially between sidewalls and gate spacers.
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14. A method of forming a silicon-on-insulator device structure, comprising in combination:
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forming a layer of pre-gate oxide on a device silicon layer;
creating a p-well region and an n-well region in the device silicon layer;
removing the pre-gate oxide layer;
forming a gate oxide layer;
forming a gate polysilicon layer;
doping the gate polysilicon layer to create a P-channel device and an N-channel device;
forming a nitride layer;
etching the nitride layer and the gate polysilicon layer;
performing body tie implants;
forming body tie spacers;
etching the body tie spacers, the gate oxide layer, and the device silicon layer;
forming a field oxide layer;
planarizing the field oxide layer;
removing the nitride layer;
forming a second polysilicon layer;
etching the second polysilicon layer and the gate polysilicon layer to form a gate;
creating gate edge profile adjustment implants in the device silicon layer to create a conduction path; and
forming source, drain, and body contacts. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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60. A method of forming a silicon-on-insulator device structure, comprising in combination:
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providing a p-well region and an n-well region in a device silicon layer and a gate polysilicon layer;
providing at least one body tie in the device silicon layer;
providing body tie spacers;
providing sidewalls;
providing a gate by shaping the gate polysilicon layer and a second polysilicon layer;
providing gate spacers;
providing at least one source in the device silicon layer;
providing at least one drain in the device silicon layer; and
providing at least one body contact in the device silicon layer, wherein the at least one body tie connects the p-well region of the device silicon layer to the at least one body contact. - View Dependent Claims (61, 62, 63)
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Specification