Embedding a JTAG host controller into an FPGA design

• US 20040001432A1
• Filed: 06/28/2002
• Published: 01/01/2004
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Telogy Networks, Inc. (Texas Instruments, Inc.)
• Original Assignee: Telogy Networks, Inc. (Texas Instruments, Inc.)
• Inventors: Wescott, Douglas Albert
• Granted Patent: US 6,983,441 B2
• Time in Patent Office: Days
• US Class Current: 370/217
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development and DSP programming, and boundary scan of targeted hardware using JTAG commands and architecture is described. The FPGA-based JTAG host controller is bussed directly into the FPGA core, bypassing the board'"'"'s JTAG communication port.

Claims

4-1. The system of claim 1, wherein

the FPGA is removable from the printed circuit board.

8. A method for configuring a field programmable gate array (FPGA) to communicate with a target hardware device using JTAG architecture, comprising:

forming an embedded JTAG host controller on a printed circuit board by placing an FPGA on a printed circuit board;

a memory array embedded in the FPGA;

communicating JTAG instructions to JTAG ports of target hardware through a JTAG logic interface in the FPGA;

interfacing with a communications bus from an external computer via a communications driver in the FPGA.

9. The method of claim 8, wherein:

the memory array is one of the following;

random access memory, read only memory, a first-in first-out buffer, an adder, a multiplier, an application specific integrated circuit, or any functionality having a known input-output transfer function.

10. The method of claim 8, wherein:

the step of interfacing with a communications bus interfaces receives program commands from software on an external computer.

11. The method of claim 8, wherein:

the memory array buffers output data sent between the targeted hardware and an external computer.

12. The method of claim 8, wherein:

the targeted hardware is one of the following;

a digital signal processor, an application specific integrated circuit, or an integrated circuit.