Shared memory multiprocessor system
First Claim
1. A multiprocessor system having a plurality of nodes, each node including at least one CPU, at least one Translation Lookaside Buffer (TLB), each associated with a respective Central Processing Unit (CPU), and a local main memory forming a part of a main memory space of the multiprocessor system, and an inter-node network, each of the nodes further comprising:
- a map table having entries corresponding to respective physical pages of said local main memory and storing correspondence between each physical page number of said physical pages and a virtual page number actually mapped to each physical page number;
network transaction generating means for generating, when a result of an address translation using a TLB indicates that a memory access request from a CPU is to be directed to a local maim memory of another node, a network transaction corresponding to said memory access request which includes a physical address to be accessed obtained from said result of the address translation using the TLB and a virtual page number designated in said memory access request from the CPU;
transaction receiving means for receiving network transactions transferred from other nodes;
checking means for checking for coincidence between a first virtual page number which is included in a received network transaction and a second virtual page number obtained through reference to said map table using a physical address included in the received memory access transaction; and
main memory access means for executing an access to said local main memory corresponding to said received network transaction when said first and second virtual page numbers are coincident.
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Accused Products
Abstract
Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.
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Citations
10 Claims
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1. A multiprocessor system having a plurality of nodes, each node including at least one CPU, at least one Translation Lookaside Buffer (TLB), each associated with a respective Central Processing Unit (CPU), and a local main memory forming a part of a main memory space of the multiprocessor system, and an inter-node network, each of the nodes further comprising:
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a map table having entries corresponding to respective physical pages of said local main memory and storing correspondence between each physical page number of said physical pages and a virtual page number actually mapped to each physical page number;
network transaction generating means for generating, when a result of an address translation using a TLB indicates that a memory access request from a CPU is to be directed to a local maim memory of another node, a network transaction corresponding to said memory access request which includes a physical address to be accessed obtained from said result of the address translation using the TLB and a virtual page number designated in said memory access request from the CPU;
transaction receiving means for receiving network transactions transferred from other nodes;
checking means for checking for coincidence between a first virtual page number which is included in a received network transaction and a second virtual page number obtained through reference to said map table using a physical address included in the received memory access transaction; and
main memory access means for executing an access to said local main memory corresponding to said received network transaction when said first and second virtual page numbers are coincident. - View Dependent Claims (2, 3, 4, 5)
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6. A multiprocessor system having a plurality of nodes, each node including at least one Central Processing Unit (CPU) at least one Translation Lookaside Buffer (TLB), each associated with a respective CPU, and a local main memory forming a part of a main memory space of the multiprocessor system, and an inter-node network, each of the nodes further comprising:
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a map table having entries corresponding to respective physical pages of said local main memory and storing correspondence between each physical page number of said physical pages and a virtual page number actually mapped to said each physical page number;
network transaction generating means for generating, when a result of an address translation using a TLB indicates that a memory access request from a CPU is to be directed to a local main memory of another node, a network transaction corresponding to said memory access request which includes a physical address to be accessed obtained from said result of the address translation using the TLB and a virtual page number designated in said memory access request from the CPU;
transaction receiving means for receiving network transactions transferred from other nodes;
checking means for checking for coincidence between a first virtual page number which is included in a received network transaction and a second virtual page number obtained through reference to said map table using a physical address included in the received memory access transaction;
main memory access means for executing an access to said local main memory corresponding to said received network transaction when said first and second virtual page numbers are coincident; and
error message generating means for informing a source of said received network transaction of an error when said first and second virtual pages are not coincident. - View Dependent Claims (7, 8, 9, 10)
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Specification