TRENCH GATE TYPE SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME

• US 20040041207A1
• Filed: 11/07/2002
• Published: 03/04/2004
• Est. Priority Date: 09/02/2002
• Status: Active Grant

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takano, Akio, Kawano, Takahiro
• Granted Patent: US 6,717,210 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench gate type semiconductor device includes a first semiconductor layer having first and second main surfaces, a second semiconductor layer of a first conductivity type as formed on the first main surface of the first semiconductor layer, a third semiconductor layer of a second conductivity type as formed on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type as formed at a surface of the third semiconductor layer, a gate electrode having a polycrystalline silicon layer being buried in a trench formed to a depth reaching the second semiconductor layer from a surface of the fourth semiconductor layer with a gate insulating film interposed therebetween and having an upper end portion protruding upwardly from a trench upper end opening while having its width greater than a width of the trench and a metal silicide film formed at an upper surface and side surfaces of the upper end portion of the polycrystalline silicon layer, a first main electrode in contact with both the fourth third semiconductor layer, and a second main electrode formed at the second main surface of the first semiconductor layer.

Claims

1. A trench gate type semiconductor device comprising:

a first semiconductor layer having first and second main surfaces;

a second semiconductor layer of a first conductivity type as formed on said first main surface of said first semiconductor layer;

a third semiconductor layer of a second conductivity type as formed on said second semiconductor layer;

a fourth semiconductor layer of the first conductivity type as formed at a surface of said third semiconductor layer;

a gate electrode having a polycrystalline silicon layer being buried in a trench formed to a depth reaching said second semiconductor layer from a surface of said fourth semiconductor layer with a gate insulating film interposed therebetween and having an upper end portion protruding upwardly from a trench upper end opening while having its width greater than a width of said trench and a metal silicide film formed at an upper surface and side surfaces of said upper end portion of said polycrystalline silicon layer;

a first main electrode in contact with both said fourth semiconductor layer and said third semiconductor layer; and

a second main electrode formed at said second main surface of said first semiconductor layer.

2. The semiconductor device according to claim 1, wherein said gate electrode is formed as a mesh-like pattern.

3. The semiconductor device according to claim 2, wherein said gate electrode is less than or equal to 1 micrometer (μ

m) in trench width in a direction of the array of said stripe portions, and wherein said metal silicide film is a titanium (Ti) silicide.

4. The semiconductor device according to claim 1, wherein said polycrystalline silicon layer is deposited as a multilayer structure of an impurity doped layer and an undoped layer, and wherein said undoped layer is completely silicidized.

5. The semiconductor device according to claim 2, wherein grooves extending from the surface of said fourth semiconductor layer and reaching said third semiconductor layer are formed between the respective stripe portions of said gate electrode, and wherein said first main electrode is in contact with both said third semiconductor layer and said fourth semiconductor layer in each groove.

6. The semiconductor device according to claim 1, wherein said semiconductor device is a metal oxide semiconductor (MOS) transistor with said first semiconductor layer as a low resistivity drain layer of the first conductivity type, with said second semiconductor layer as a high resistivity drain layer, with said third semiconductor layer as a base layer, and with said fourth semiconductor layer as a source layer.

7. The semiconductor device according to claim 1, wherein said semiconductor device is an insulated gate bipolar transistor with said first semiconductor layer as a collector layer of the second conductivity type, with said second semiconductor layer as a first base layer, with said third semiconductor layer as a second base layer, and with said fourth semiconductor layer as an emitter layer.

8. A method of fabricating a trench gate type semiconductor device, said method comprising:

forming a second semiconductor layer of a first conductivity type on a first main surface of a first semiconductor layer having first and second main surfaces;

doping an impurity into a surface of said second semiconductor layer to thereby form a third semiconductor layer of a second conductivity type;

doping an impurity into a surface of said third semiconductor layer to form a fourth semiconductor layer of the first conductivity type;

forming a trench extending from a surface of said fourth semiconductor layer and penetrating said third semiconductor layer to have a depth reaching said second semiconductor layer;

after having formed a gate insulating film on inner surfaces of said trench, depositing over said fourth semiconductor layer a polycrystalline silicon layer in such a manner as to completely bury said trench;

etching said polycrystalline silicon layer to form a gate electrode having its main part buried in said trench and an upper end portion protruding upwardly from a trench upper end opening while having a width greater than a width of said trench;

forming a metal silicide film at an upper surface and side surfaces of said upper end portion of said gate electrode; and

forming a first main electrode in contact with both said fourth semiconductor layer and said third semiconductor layer and a second main electrode in contact with said second main surface of said first semiconductor layer, respectively.

9. The method according to claim 8, wherein said gate electrode is formed as a mesh-like pattern.

10. The method according to claim 9, wherein said gate electrode is 1 μ

m or less in trench width in a direction of the array of said stripe portions, and wherein said metal silicide film is a Ti silicide.

11. The method according to claim 8, wherein said polycrystalline silicon layer is deposited as a multilayer structure of an impurity doped layer and an undoped layer, and wherein said undoped layer is completely silicidized.

12. The method according to claim 8, further comprising:

forming, prior to formation of said first main electrode, a groove extending from the surface of said fourth semiconductor layer and reaching said third semiconductor layer.

13. The method according to claim 8, wherein said semiconductor device is a MOS transistor with said first semiconductor layer as a low resistivity drain layer of the first conductivity type, with said second semiconductor layer as a high resistivity drain layer, with said third semiconductor layer as a base layer, and with said fourth semiconductor layer as a source layer.

14. The method according to claim 8, wherein said semiconductor device is an insulated gate bipolar transistor with said first semiconductor layer as a collector layer of the second conductivity type, with said second semiconductor layer as a first base layer, with said third semiconductor layer as a second base layer, and with said fourth semiconductor layer as an emitter layer.