Physical layer apparatus compliant to serial and parallel ATA interfaces

• US 20040044802A1
• Filed: 05/06/2003
• Published: 03/04/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Wang, Tse-Hsien, Chiang, Chinyi
• Granted Patent: US 7,159,055 B2
• Time in Patent Office: Days
• US Class Current: 710/1
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A physical layer apparatus compliant for both serial and parallel ATA interfaces is devised. The physical layer apparatus includes a serial ATA physical layer circuit, a channel selection unit and a channel selection controller. The channel selection unit is connected to a media access controller of a host through a first IDE bus. The channel selection unit is further selectively connected to a serial ATA device through the serial ATA physical circuit or connected to a parallel ATA device through second IDE bus. Therefore, the media access controller of the host can selectively access the serial ATA device and the parallel ATA device through the channel selection unit under the control of the channel selection controller.

Claims

1. A physical layer apparatus for ATA interface, comprising

a serial ATA physical layer circuit through which at least one serial ATA device is connected;

a channel selection unit connected to a media access controller of a host through a first IDE bus and selectively connected to one of said serial ATA physical layer circuit and a second IDE bus through an accessing channel; and

a channel selection controller connected to said channel selection unit and used to control said channel selection unit for connecting to one of said serial ATA physical layer circuit and said second IDE bus.

2. The physical layer apparatus for ATA interface as in claim 1, further comprising a detection circuit connected to said channel selection controller, wherein said detection circuit detects a connection state of said serial ATA device with respect to said serial ATA physical layer circuit and drives said channel selection controller to generate a control signal according to said connection state of said serial ATA device, said accessing channel of said channel selection unit being controlled by said control signal such that said media access controller is selectively connected to one of said serial ATA physical layer circuit and said second IDE bus through said channel selection unit and said accessing channel.

3. The physical layer apparatus for ATA interface as in claim 1, wherein said channel selection device comprises a selection switch and a voltage level adapter.

4. The physical layer apparatus for ATA interface as in claim 3, wherein said selection switch is a multiplexer.

5. The physical layer apparatus for ATA interface as in claim 3, wherein said voltage level adapter adapts a voltage level of said first IDE bus to that of the serial ATA device when said channel selection unit is connected to said serial ATA physical layer circuit through said accessing channel.

6. The physical layer apparatus for ATA interface as in claim 3, wherein said voltage level adapter adapts said voltage level of said first IDE bus to that of the parallel ATA device when said channel selection unit is connected to said second IDE bus through said accessing channel.

7. The physical layer apparatus for ATA interface as in claim 1, wherein said accessing channel of said channel selection unit is controlled by a software.

8. The physical layer apparatus for ATA interface as in claim 1, further comprising a manual switch connected to said channel selection controller and used to change a setting of said channel selection controller.

9. The physical layer apparatus for ATA interface as in claim 2, further comprising a manual switch to set an automatic detection mode for channel selection, wherein an accessing channel is selected between said serial ATA physical layer circuit and said second IDE bus.

10. The physical layer apparatus for ATA interface as in claim 1, wherein said physical layer apparatus is integrated into a discrete physical layer chip.

11. The physical layer apparatus for ATA interface as in claim 10, wherein said discrete physical layer chip is directly mounted on a motherboard.

12. The physical layer apparatus for ATA interface as in claim 10, wherein said discrete physical layer chip is integrated into a controller card.