Memory management of local variables

• US 20040078523A1
• Filed: 07/31/2003
• Published: 04/22/2004
• Est. Priority Date: 07/31/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard, Kuusela, Maija, DʼInverno, Dominique
• Granted Patent: US 7,203,797 B2
• Time in Patent Office: Days
• US Class Current: 711/128
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

Claims

1. A processor, comprising:

a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate, each method using its own set of local variables; and

a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

2. The processor of claim 1 wherein the data memory includes a plurality of lines and a valid bit and a dirty bit associated with each line, and wherein upon completion of a method, the local variables associated with said completed method continue to be marked as valid and not copied back to a main memory even though the lines in which the completed method'"'"'s local variables are stored are marked as valid and dirty.

3. The processor of claim 1 wherein when a new method is called, the local variables associated with the called method use data memory space previously used by local variables associated with completed methods without generating a miss.

4. The processor of claim 1 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.

5. The processor of claim 1 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid without causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.

6. The processor of claim 1 wherein the data memory containing the local variables has a higher priority during hit/miss determinations than all other ways.

7. The processor of claim 1 wherein, if said way storing said local variables does not have sufficient capacity to store the local variables, then at least some local variables are stored in the 2-way set associative cache.

8. The processor of claim 1 including a global valid bit that indicates whether the local variables stored in the data memory is valid or not and a valid bit for each of a plurality of entries associated with the data memory indicating whether each entry holds a valid local variable.

9. A cache subsystem, comprising:

a multi-way set associative cache; and

a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

10. The cache subsystem of claim 9 wherein the data memory includes a plurality of lines and a valid bit and a dirty bit associated with each line, and wherein upon completion of a method, the local variables associated with said completed method continue to be marked as valid and not copied back to a main memory even though the lines in which the completed method'"'"'s local variables are stored are marked as valid and dirty.

11. The cache subsystem of claim 9 wherein when a new method is called, the local variables associated with the called method use data memory space previously used by local variables associated with completed methods without generating a miss.

12. The cache subsystem of claim 9 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.

13. The cache subsystem of claim 9 wherein the data memory includes a plurality of lines, each line being marked as either valid or invalid, and when a line is marked as invalid and data memory hit/miss occurs, a targeted line is marked as valid without causing a line fetch from external memory to occur, wherein a hit/miss indicates that a targeted address hits in the data memory but targeted data is not stored in the data memory.

14. The cache subsystem of claim 9 wherein the data memory containing the local variables has a higher priority during hit/miss determinations than all other ways.

15. The cache subsystem of claim 9 wherein, if said way storing said local variables does not have sufficient capacity to store the local variables, then at least some local variables are stored in the 2-way set associative cache.

16. The cache subsystem of claim 15 wherein said local variables comprise local variables used in a stack-based instruction set.

17. A cache subsystem, comprising:

a multi-way set associative cache; and

a means for holding a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

18. The cache subsystem of claim 17 further including a means for locking said local variables in said cache subsystem.

19. The cache subsystem of claim 17 further including a means for preventing said local variables from being written to external memory upon completion of a method that uses said local variables.

20. A method, comprising:

programming a register to define a contiguous block of memory in a cache subsystem; and

storing local variables associated with executing methods in the contiguous block of memory.

21. The method of claim 20 further comprising marking lines in the block as valid and completing a method while continuing to mark the lines as valid and not copying the local variables associated with the completed method to a main memory.

22. The method of claim 20 further comprising invoking a new method and writing local variables associated with the new method to cache memory space previously used by local variables associated with completed methods without generating a miss.

23. The method of claim 20 further comprising configuring a global valid bit to indicate whether the local variables are collectively valid and configuring a valid bit for each of a plurality of entries in the block to indicate whether each entry contains valid data.