Method and apparatus for automatic configuration of multiple on-chip interconnects

• US 20040128341A1
• Filed: 12/27/2002
• Published: 07/01/2004
• Est. Priority Date: 12/27/2002
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Weber, Wolf-Dietrich, Chou, Chien-Chun, Synek, Kamil
• Granted Patent: US 7,603,441 B2
• Time in Patent Office: Days
• US Class Current: 709/200
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A method and apparatus for automatic configuration of multiple on-chip interconnects have been described. In one embodiment, the invention reduces the configuration time of several on-chip network features, and also ensures that these features are configured correctly to minimize errors in a design.

Claims

1. A method comprising:

determining a topology of a network;

configuring a plurality of bridge agents based on said topology;

configuring a system address map of said network; and

configuring a plurality of signals.

2. The method of claim 1 wherein said plurality of signals are selected from the group consisting of flag signals, error signals, and reset signals.

3. The method of claim 1 wherein said network is an on-chip network.

4. The method of claim 3 wherein one or more of said plurality of bridge agents are operating at different frequencies.

5. A machine-readable medium having stored thereon instructions, which when executed performs the method of claim 1.

6. A processing system comprising a processor, which when executing a set of instructions performs the method of claim 1.

7. A method comprising:

inputting a network configuration;

determining a network topology from said network configuration;

checking said network topology for a connectivity selected from the group consisting of a fully connected network, and a tree network;

checking for correct configuration of bridge agents in said network configuration based on said network topology;

checking for correct configuration of an address entity selected from the group consisting of address map, address matching registers in said bridge agents, and address matching registers in a plurality of core agents; and

checking for correct signal entities selected from the group consisting of configuration of error signals between said bridge agents, routing of error signals between said bridge agents, configuration of flag signals between said bridge agents, and routing of flag signals between said bridge agents.

8. The method of claim 7 wherein said network topology is an on-chip network topology.

9. The method of claim 8 wherein one or more of said plurality of agents selected from the group consisting of bridge, and core are operating at different frequencies.

10. A machine-readable medium having stored thereon instructions, which when executed performs the method of claim 7.

11. A processing system comprising a processor coupled to a memory, which when executing a set of instructions performs the method of claim 7.

12. A method comprising:

determining a plurality of address maps for a plurality of networks on a chip;

determining a network topology for said chip and said plurality of networks;

configuring a plurality of bridge agents to interconnect said plurality of networks on said chip.

18. A machine-readable medium having stored thereon instructions, which when executed performs the method of claim 12.

19. A processing system comprising a processor couple to a memory, which when executing a set of instructions performs the method of claim 12.

13. The method of 12 wherein said bridge agents each has a configuration feature selected from the group consisting of bridge forwarding, component identification, connection identifier support, error handling, interrupt handling, software generated reset, and timeout of requests.

14. The method of 12 wherein said bridge agents each has an interface feature selected from the group consisting of address space extension, byte enable extension, burst extension, connection identifier extension, data handshake extension, thread extension, write response extension, flag extension, error extension, control extension, and status extension.

15. The method of 12 wherein an address map of a specific one of said plurality of bridge agents includes an address map of a network to which said specific bridge agent is attached and an address map to all other attached networks.

16. The method of 15 wherein one or more of said plurality of bridge agents directly connected to each other have mutually exclusive address regions.

17. The method of 15 wherein said plurality of core agents have address regions that do not overlap.

20. A method for configuring on-chip network connections, the method comprising:

configuring one or more bridge agents based upon said network'"'"'s topology;

configuring a system address map for one or more micro-networks;

configuring and routing flag signals on a per core basis for one or more cores;

configuring and routing error signals on a per core basis for one or more cores; and

configuring and routing reset signals.

21. The method of claim 20 further comprising differing clock frequencies for entities selected from the group consisting of said one or more bridge agents, said one or more micro-networks, and said one or more cores.

22. The method of claim 20 wherein said system address map encompasses all address regions of all said one or more bridge agents in possible communication with each other on said on-chip network.

23. The method of claim 22 further comprising configuring said one or more bridge agents respective address matchers from said address map.

24. The method of claim 23 further comprising taking into account that a specific one or more bridge agents'"'"' register resides in a same address space as said specific one or more bridge agents'"'"' on-chip interconnect.

25. The method of claim 20 wherein said one or more bridge agents that are not in a acyclic path tree of said network'"'"'s topology do not forward said error signals.

26. The method of claim 20 further comprising wherein any said reset signals routed to said one or more bridge agents are configured such that a specfic micro-network, associated with a specific said one or more bridge agents, that comes out of a reset last drives a reset across a connecting agent bridge.

27. The method of claim 20 wherein address matchers for said one or more bridge agents that directly connect two on-chip networks match mutually exclusive address regions.

28. The method of claim 20 wherein for any network topology address matchers of any two core agents do not overlap.

29. The method of claim 20 wherein if a specific one of said one or more bridge agents (A) does not bridge a specific one of said error signals (E) then another said one or more bridge agents (B) connected to said specific one of said one or more bridge agents (A) does not bridge said specific one of said error signals (E).

30. A machine-readable medium having stored thereon instructions, which when executed performs the method of claim 20.

31. A processing system comprising a processor couple to a memory, which when executing a set of instructions performs the method of claim 20.

32. An apparatus comprising:

means for determining a topology of a network;

means for configuring a plurality of bridge agents based on said topology;

means for configuring a system address map of said network; and

means for configuring a plurality of signals.

33. The apparatus of claim 32 further comprising means for checking said configuration of said plurality of signals.