Integrated circuit with improved channel stress properties and a method for making it

• US 20040235236A1
• Filed: 05/21/2003
• Published: 11/25/2004
• Est. Priority Date: 05/21/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Armstrong, Mark, Hoffmann, Thomas, Auth, Chris, Cea, Stephen
• Granted Patent: US 7,045,408 B2
• Time in Patent Office: Days
• US Class Current: 438/231
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.

Claims

1. An integrated circuit comprising:

a PMOS transistor and an NMOS transistor formed on a semiconductor substrate;

a silicate glass layer formed on only the PMOS transistor or the NMOS transistor; and

an etch stop layer formed on the silicate glass layer.

2. The integrated circuit of claim 1 wherein the etch stop layer is in tension and the silicate glass layer is formed on the PMOS transistor.

3. The integrated circuit of claim 1 wherein the etch stop layer is in compression and the silicate glass layer is formed on the NMOS transistor.

4. The integrated circuit of claim 1 wherein the silicate glass layer has a thickness of between about 100 and about 2,000 angstroms and comprises a silicon dioxide layer;

and the etch stop layer has a thickness of between about 100 and about 1,500 angstroms and comprises silicon nitride.

5. The integrated circuit of claim 2 wherein the NMOS transistor further comprises:

a gate electrode that has a top surface, a first side surface and a second side surface, the gate electrode positioned between a source region and a drain region; and

first and second spacers located along the first and second side surfaces and on the source and drain regions; and

wherein the etch stop layer is formed on the first and second spacers and on the source and drain regions, but is not formed on the top surface of the gate electrode.

6. An integrated circuit comprising:

a PMOS transistor and an NMOS transistor formed on a semiconductor substrate, the NMOS transistor having a gate electrode that has a top surface, a first side surface and a second side surface;

a silicate glass layer formed on only the PMOS transistor; and

an etch stop layer formed on the silicate glass layer and along the first side surface and the second side surface of the gate electrode, but not formed on the top surface of the gate electrode.

7. The integrated circuit of claim 6 wherein the silicate glass layer has a thickness of between about 100 and about 2,000 angstroms and comprises a silicon dioxide layer.

8. The integrated circuit of claim 7 wherein the etch stop layer has a thickness of between about 100 and about 1,500 angstroms and comprises silicon nitride.

9. A method for forming an integrated circuit comprising:

forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate;

forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure; and

forming an etch stop layer on the silicate glass layer.

10. The method of claim 9 wherein the etch stop layer is in tension and the silicate glass layer is formed on the PMOS transistor structure.

11. The method of claim 9 wherein the etch stop layer is in compression and the silicate glass layer is formed on the NMOS transistor structure.

12. The method of claim 9 wherein the silicate glass layer has a thickness of between about 100 and about 2,000 angstroms and comprises a silicon dioxide layer.

13. The method of claim 10 further comprising:

forming a gate electrode that has a top surface, a first side surface and a second side surface, the gate electrode positioned between a source region and a drain region;

forming first and second spacers along the first and second side surfaces and on the source and drain regions;

forming the etch stop layer on the first and second spacers, on the source and drain regions, and on the top surface of the gate electrode; and

removing the etch stop layer from the top surface of the gate electrode.

14. The method of claim 13 wherein the etch stop layer is removed from the top surface of the gate electrode using a chemical mechanical polishing process.

15. The method of claim 14 wherein the etch stop layer has a thickness of between about 100 and about 1,500 angstroms and comprises silicon nitride.

16. A method for forming an integrated circuit comprising:

forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, the NMOS transistor structure having a gate electrode that has a top surface, a first side surface and a second side surface;

forming a silicate glass layer on only the PMOS transistor structure;

forming an etch stop layer on the silicate glass layer and along the first side surface and the second side surface of the gate electrode, and on the top surface of the gate electrode; and

removing the etch stop layer from the top surface of the gate electrode.

17. The method of claim 16 wherein the etch stop layer is removed from the top surface of the gate electrodes using a chemical mechanical polishing process.

18. The method of claim 16 wherein the silicate glass layer has a thickness of between about 100 and about 2,000 angstroms and comprises silicon dioxide.

19. The method of claim 16 wherein the etch stop layer has a thickness of between about 100 and about 1,500 angstroms and comprises silicon nitride.

20. The method of claim 16 wherein the silicate glass layer is formed on only the PMOS transistor structure by forming the silicate glass layer on both the PMOS transistor structure and the NMOS transistor structure, masking the silicate glass layer where it covers the PMOS transistor structure, and removing the silicate glass layer where it covers the NMOS transistor structure.