Light emitting device methods

• US 20040259285A1
• Filed: 03/05/2004
• Published: 12/23/2004
• Est. Priority Date: 04/15/2003
• Status: Active Grant

• Current Assignee: Formosa Epitaxy Incorporated (Ennostar, Inc.)
• Original Assignee: Luminus Devices Incorporated (Sanan Optoelectronics Company Limited)
• Inventors: Erchak, Alexei A., Brown, Michael Gregory, Graff, John W., Duncan, Scott W., Minsky, Milan Singh
• Granted Patent: US 7,074,631 B2
• Time in Patent Office: Days
• US Class Current: 438/47
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer
• CPC Class Codes: Y10S 438/956 Making multiple wavelength emissive device

Abstract

Light-emitting device methods are disclosed.

Claims

1. A method of making a light-emitting device, the method comprising:

disposing a planarization layer on a surface of a layer of semiconductor material;

disposing a lithography layer on a surface of the planarization layer; and

performing nanolithography to remove at least a portion of the planarization layer, at least a portion of the lithography layer and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern.

2. The method of claim 1, wherein performing nanolithography includes forming indentations in the lithography layer.

3. The method of claim 2, further comprising heating the lithography layer while forming the indentations in the lithography layer.

4. The method of claim 3, wherein the lithography layer is cooled after forming the indentations.

5. The method of claim 2, further comprising UV-curing the lithography layer while forming the indentations in the lithography layer.

6. The method of claim 2, wherein the indentations from the lithography layer correspond to the portion of the lithography layer removed during nanolithography.

7. The method of claim 1, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

8. The method of claim 7, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

9. The method of claim 8, wherein the portion of the layer of semiconductor material removed during nanolithography forms the pattern in the surface of the layer of semiconductor material.

10. The method of claim 1, further comprising, after removing portions of the lithography and planarization layers, depositing a material on exposed portions of the layer of semiconductor material.

11. The method of claim 10, further comprising depositing the material on an exposed upper surface of the lithography layer.

12. The method of claim 11, further comprising removing the portions of lithography layer having the material deposited thereon.

13. The method of claim 12, further comprising removing the portions of the planarization layer corresponding to the portions of the lithography layer having the material deposited thereon.

14. The method of claim 12, further comprising removing portions of the layer of semiconductor material that do not have the material deposited thereon to form the pattern in the surface of the layer of semiconductor material.

15. The method of claim 10, wherein the material comprises a metal.

16. The method of claim 15, wherein the material comprises at least one metal selected from the group consisting of aluminum, nickel, titanium and tungsten.

17. The method of claim 1, wherein performing nanolithography includes forming indentations in the lithography layer, and the method further comprises coating at least some of the indentations in the lithography layer with an etch resistant material.

18. The method of claim 17, wherein the etch resistant material is disposed on the surface of the lithography layer, and the etch resistant material is then etched to expose an upper surface of the lithography layer while keeping some of the etch resistant material in the indentations in the lithography layer.

19. The method of claim 18, wherein the etch resistant material is spin coated onto the lithography layer.

20. The method of claim 18, wherein the etch resistant material comprises a silicon doped polymer.

21. The method of claim 18, wherein the portions of the lithography layer that are not coated with the etch resistant material correspond to the portion of the lithography layer removed during nanolithography.

22. The method of claim 21, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

23. The method of claim 22, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

24. The method of claim 23, wherein the portion of the layer of semiconductor material removed during nanolithography forms the pattern in the surface of the layer of semiconductor material.

25. The method of claim 1, further comprising, after performing nanolithography, removing remaining portions of the planarization layer and remaining portions of the lithography layer.

26. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, disbanding the layer of semiconductor material from a substrate.

27. The method of claim 26, wherein disbanding the layer of semiconductor material from the substrate includes a laser liftoff process.

28. The method of claim 26, wherein disbanding the layer of semiconductor material includes etching the substrate.

29. The method of claim 26, wherein disbonding the layer of semiconductor material includes lapping the substrate.

30. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, etching the surface of the layer of semiconductor material.

31. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, performing chemical-mechanical polishing on the surface of the layer of semiconductor material.

32. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, lapping the surface of the layer of semiconductor material.

33. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, polishing the surface of the layer of semiconductor material.

34. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, grinding the surface of the layer of semiconductor material.

35. The method of claim 1, further comprising, after performing nanolithography, depositing an electrical contact on the surface of the layer of semiconductor material.

36. The method of claim 1, wherein the semiconductor material comprises a III-V semiconductor material.

37. The method of claim 36, wherein the III-V semiconductor material is doped.

38. The method of claim 37, wherein the III-V semiconductor material is n-doped.

39. The method of claim 1, wherein the semiconductor material is selected from the group consisting of n-doped GaN, n-doped AlInGaN, n-doped AlGaN, n-doped InGaN and combinations thereof.

40. The method of claim 1, wherein the lithography layer comprises a polymer.

41. The method of claim 40, wherein the polymer comprises a UV-curable polymer.

42. The method of claim 1, wherein the lithography layer is at least about one nanometer thick.

43. The method of claim 1, wherein the lithography layer is at most about one micron thick.

44. The method of claim 1, wherein the planarization layer comprises a polymer.

45. The method of claim 41, wherein the polymer comprises a high-viscosity formable polymer.

46. The method of claim 1, wherein the planarization layer is at least about 100 nanometers thick.

47. The method of claim 1, wherein the planarization layer is at most about five microns thick.

48. The method of claim 1, wherein the layer of semiconductor material comprises a layer of n-doped semiconductor material, and the layer of semiconductor material is supported by a layer of p-doped semiconductor material and an active region of semiconductor material, the active region of semiconductor material being between the layer of n-doped semiconductor material and the layer of p-doped semiconductor material.

49. The method of claim 1, wherein the light-emitting device is selected from the group consisting of light-emitting diodes, lasers, optical amplifiers, and combinations thereof.

50. The method of claim 1, wherein the light-emitting device comprises a light emitting diode.

51. The method of claim 1, wherein the light-emitting device is selected from the group consisting of OLEDs, flat surface-emitting LEDs, HBLEDs, and combinations thereof.

52. The method of claim 1, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a periodic pattern.

53. The method of claim 52, wherein the surface of the layer of semiconductor material is rough.

54. The method of claim 1, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a nonperiodic pattern.

55. The method of claim 1, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per square centimeter.

56. The method of claim 1, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per 6.25 square centimeters.

57. The method of claim 1, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has an RMS roughness of at most about 50 nanometers.

58. The method of claim 1, wherein, before performing nanolithography, the planarization layer, the lithography layer and the layer of semiconductor material are in the form of a wafer.

59. The method of claim 1, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, performing at least one process selected from the group consisting of etching the surface of the layer of semiconductor material, chemical-mechanical polishing the surface of the layer of semiconductor material, lapping the surface of the layer of semiconductor material, polishing the surface of the layer of semiconductor material, and grinding the surface of the layer of semiconductor material.

60. The method of claim 1, further comprising, prior to depositing the lithography layer, flattening an upper surface of the planarization layer.

61. A method of making a light-emitting device, the method comprising:

providing an article that comprises a layer of semiconductor material, and a planarization layer supported by the layer of semiconductor material; and

performing nanolithography to remove at least a portion of the planarization layer and at least a portion of the layer of semiconductor material, thereby forming a dielectric function in the surface of the layer of semiconductor material that varies spatially according to a pattern.

62. The method of claim 61, wherein the article further comprises a lithography layer supported by the planarization layer.

63. The method of claim 62, wherein performing nanolithography removes at least a portion of the lithography layer.

64. The method of claim 63, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

65. The method of claim 64, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

66. The method of claim 62, wherein the article further comprises an etch mask layer.

67. The method of claim 66, wherein the etch mask layer is between the layer of semiconductor material and the planarization layer.

68. The method of claim 66, wherein performing nanolithography removes at least a portion of the etch mask layer.

69. The method of claim 61, further comprising, after removing portions of the lithography and planarization layers, depositing a material on exposed portions of the layer of semiconductor material.

70. The method of claim 69, further comprising depositing the material on the an upper surface of the lithography layer.

71. The method of claim 70, further comprising removing the portions of lithography layer having the material deposited thereon.

72. The method of claim 71, further comprising removing the portions of the planarization layer corresponding to the portions of the lithography layer having the material deposited thereon.

73. The method of claim 72, further comprising removing portions of the layer of semiconductor material that do not have the material deposited thereon to form the pattern in the surface of the layer of semiconductor material.

74. The method of claim 69, wherein the material comprises a metal.

75. The method of claim 74, wherein the material comprises at least one metal selected from the group consisting of aluminum, nickel, titanium and tungsten.

76. The method of claim 61, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

77. The method of claim 76, wherein performing nanolithography includes forming indentations in the lithography layer, and the method further comprises coating at least some of the indentations in the lithography layer with an etch resistant material.

78. The method of claim 77, wherein the etch resistant material is disposed on the surface of the lithography layer, and the etch resistant material is then etched to expose an upper surface of the lithography layer while keeping some of the etch resistant material in the indentations in the lithography layer.

79. The method of claim 77, wherein the etch resistant material is spin coated onto the lithography layer.

80. The method of claim 77, wherein the etch resistant material comprises a silicon doped polymer.

81. The method of claim 77, wherein the portions of the lithography layer that are not coated with the etch resistant material correspond to the portion of the lithography layer removed during nanolithography.

82. The method of claim 80, wherein the portion of the planarization layer removed during nanolithography corresponds to the portion of the lithography layer removed during nanolithography.

83. The method of claim 81, wherein the portion of the layer of semiconductor material removed during nanolithography corresponds to the portion of the planarization layer removed during nanolithography.

84. The method of claim 82, wherein the portion of the layer of semiconductor material removed during nanolithography forms the pattern in the surface of the layer of semiconductor material.

85. The method of claim 61, further comprising, before supporting the planarization layer with the layer of semiconductor material, disbonding the layer of semiconductor material from a substrate.

86. The method of claim 85, wherein disbonding the layer of semiconductor material from the substrate includes a laser liftoff process.

87. The method of claim 85, wherein disbonding the layer of semiconductor material includes etching the substrate.

88. The method of claim 85, wherein disbonding the layer of semiconductor material includes lapping the substrate.

89. The method of claim 61, further comprising, before supporting the planarization layer with the layer of semiconductor material, etching the surface of the layer of semiconductor material.

90. The method of claim 61, further comprising, before supporting the planarization layer with the layer of semiconductor material, performing chemical-mechanical polishing on the surface of the layer of semiconductor material.

91. The method of claim 61, further comprising, before supporting the planarization layer with the layer of semiconductor material, lapping the surface of the layer of semiconductor material.

92. The method of claim 61, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, polishing the surface of the layer of semiconductor material.

93. The method of claim 61, further comprising, before disposing the planarization layer on the surface of the layer of semiconductor material, grinding the surface of the layer of semiconductor material.

94. The method of claim 61, wherein the semiconductor material comprises a III-V semiconductor material.

95. The method of claim 94, wherein the III-V semiconductor material is doped.

96. The method of claim 95, wherein the III-V semiconductor material is n-doped.

97. The method of claim 61, wherein the semiconductor material is selected from the group consisting of n-doped GaN, n-doped AlInGaN, n-doped AlGaN, n-doped InGaN and combinations thereof.

98. The method of claim 61, wherein the light-emitting device is selected from the group consisting of light-emitting diodes, lasers, optical amplifiers, and combinations thereof.

99. The method of claim 61, wherein the light-emitting device comprises a light emitting diode.

100. The method of claim 61, wherein the light-emitting device is selected from the group consisting of OLEDs, flat surface-emitting LEDs, HBLEDs, and combinations thereof.

101. The method of claim 61, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a periodic pattern.

102. The method of claim 61, wherein the dielectric function in the surface of the layer of semiconductor material varies spatially according to a nonperiodic pattern.

103. The method of claim 61, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per square centimeter.

104. The method of claim 61, wherein, before disposing the planarization layer on the surface of the layer of semiconductor material, the surface of the layer of semiconductor material has a flatness of at most about 10 microns per 6.25 square centimeters.

105. The method of claim 61, wherein, before supporting the planarization layer with the layer of semiconductor material, the surface of the layer of semiconductor material has an RMS roughness of at most about 50 nanometers.

106. The method of claim 61, further comprising, prior to depositing the lithography layer, flattening an upper surface of the planarization layer.