Articles of manufacture and wafer processing apparatuses

• US 20050007133A1
• Filed: 08/03/2004
• Published: 01/13/2005
• Est. Priority Date: 08/21/1998
• Status: Active Grant

• Current Assignee: David R. Hembree
• Original Assignee: David R. Hembree
• Inventors: Hembree, David R.
• Granted Patent: US 7,148,718 B2
• Time in Patent Office: Days
• US Class Current: 324/754.80
• CPC Class Codes: H01L 21/67248 Temperature monitoring
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring

Abstract

The present invention includes an electronic device workpiece processing apparatus and method of communicating signals within an electronic device workpiece processing apparatus. One embodiment of s an electronic device workpiece processing apparatus includes a chuck including a surface, an electrical coupling adjacent the surface, and electrical interconnect configured to connect with the electrical coupling of the chuck and conduct a signal within the chuck; an intermediate member having a first surface and a second surface and the intermediate member including: an electrical coupling adjacent the first surface and configured to couple with the electrical coupling of the chuck; an electrical coupling adjacent the second surface; and an electrical interconnect configured to connect the electrical coupling adjacent the first surface and the electrical coupling adjacent the second surface; and an electronic device workpiece configured to couple with the second surface of the intermediate member, the electronic device workpiece including a sensor and an electrical coupling configured to provide electrical connection of the sensor with the electrical coupling of the second surface of the intermediate member.

Claims

1-13. -13. (cancel)

14. An article of manufacture comprising:

an electronic device wafer processing intermediate member adapted to receive an electronic device wafer having an electrical coupling and couple with a chuck having an electrical coupling, the intermediate member comprising;

an electrical interconnect configured to electrically connect the electrical coupling of the electronic device wafer with the electrical coupling of the chuck; and

wherein the intermediate member is configured to support the electronic device wafer comprising a plurality of integrated circuit dies being fabricated.

15. The article according to claim 14 wherein the intermediate member includes a plurality of electrical interconnects configured to electrically connect a plurality of electrical couplings of an electronic device wafer and a chuck.

16. The article according to claim 14 wherein the electrical interconnect comprises a pogo pin.

17. The article according to claim 14 wherein the electrical interconnect comprises a wire.

53. The article according to claim 14 wherein the intermediate member comprises a substantially electrically nonconductive material.

18-52. -52. (cancel)

54. A wafer processing apparatus comprising:

an electronic device wafer comprising a sensor and an electrical coupling in electrical communication with the sensor; and

an intermediate member comprising;

a first surface configured to support substantially an entirety of the electronic device wafer;

a first electrical coupling adjacent to the first surface and configured to electrically connect with the electrical coupling of the electronic device wafer;

a second surface opposite to the first surface;

a second electrical coupling adjacent to the second surface and configured to electrically connect with an electrical coupling of a chuck of the wafer processing apparatus; and

an electrical interconnect configured to electrically connect the first electrical coupling with the second electrical coupling and to communicate electrical signals between the first electrical coupling and the second electrical coupling; and

wherein the sensor is in electrical communication with the first electrical coupling, the second electrical coupling and the electrical interconnect.

55. The apparatus of claim 54 wherein the wafer has a surface, and an outwardly exposed surface of the electrical coupling of the wafer is substantially coplanar with the surface of the wafer.

56. The apparatus of claim 54 wherein the intermediate member comprises a substantially electrically nonconductive material.

57. The apparatus of claim 54 wherein the intermediate member includes a plurality of electrical interconnects configured to electrically connect a plurality of electrical couplings of the wafer and the chuck.

58. The apparatus of claim 54 wherein the electrical interconnect comprises a pogo pin.

59. The apparatus of claim 54 wherein the electrical interconnect comprises a wire.

67. The apparatus of claim 54 wherein the intermediate member is configured to expose the wafer to a processing environment.

68. The apparatus of claim 54 further comprising a processing area configured to process the wafer supported using the intermediate member.

69. The apparatus of claim 54 wherein the wafer processing apparatus is configured to process the wafer supported using the intermediate member.

70. The apparatus of claim 54 wherein the wafer comprises a semiconductive wafer.

71. The apparatus of claim 54 wherein the electronic device wafer comprises a plurality of integrated circuit dies prior to singulation of at least one of the dies at a subsequent moment in time.

60. A wafer processing apparatus comprising:

an intermediate member comprising an electrical interconnect configured to electrically connect an electrical coupling of an electronic device wafer with an electrical coupling of a chuck of the wafer processing apparatus, and wherein the electrical interconnect is configured to communicate electrical signals intermediate the electrical coupling of the wafer and the electrical coupling of the chuck.

61. The apparatus of claim 60 further comprising the electronic device wafer comprising the electrical coupling configured to electrically connect with the electrical interconnect of the intermediate member.

62. The apparatus of claim 61 wherein the wafer has a surface, and an outwardly exposed surface of the electrical coupling of the wafer is substantially coplanar with the surface of the wafer.

63. The apparatus of claim 60 wherein the intermediate member comprises a substantially electrically nonconductive material.

64. The apparatus of claim 60 wherein the intermediate member includes a plurality of electrical interconnects configured to electrically connect a plurality of electrical couplings of the wafer and the chuck.

65. The apparatus of claim 60 wherein the electrical interconnect comprises a pogo pin.

66. The apparatus of claim 60 wherein the electrical interconnect comprises a wire.

72. The apparatus of claim 60 wherein the intermediate member is configured to support a wafer for processing within the wafer processing apparatus.

73. The apparatus of claim 60 wherein the intermediate member is configured to expose a wafer to a processing environment within the wafer processing apparatus.

74. The apparatus of claim 60 further comprising a processing area configured to process a wafer supported using the intermediate member.

75. The apparatus of claim 60 wherein the wafer processing apparatus is configured to process a wafer supported using the intermediate member.

76. The apparatus of claim 60 wherein the wafer comprises a semiconductive wafer.

77. The apparatus of claim 61 wherein the electronic device wafer comprises a plurality of integrated circuit dies prior to singulation of at least one of the dies at a subsequent moment in time.