Method and circuit for determining the response curve knee point in active pixel image sensors with extended dynamic range
First Claim
1. An image array pixel comprising:
- a charge sharing node; and
a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node.
2 Assignments
0 Petitions
Accused Products
Abstract
An apparatus and method for measuring the breakpoint of a response curve representing the voltage output of an image array having an extended dynamic range. By flooding a light-opaque pixel with a charge and then applying an intermediate reset voltage to the pixel, the signal is read from the pixel and stored. The full reset voltage is applied to the pixel, and then the signal in the pixel is read and stored. The voltage output difference is the difference between the first and second stored signal. The voltage output difference is then used to determine the voltage of the knee point. Further, a conventional saturated pixel can be reset with an intermediate reset just prior to readout. The resulting signal can then be used to determine the voltage of the knee point.
-
Citations
70 Claims
-
1. An image array pixel comprising:
-
a charge sharing node; and
a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A pixel circuit, comprising:
-
a photo sensor;
a storage node for receiving charges from said photo sensor; and
a reset transistor for resetting said storage node, said reset transistor being switchably coupled to a first and second voltage level. - View Dependent Claims (9, 10, 11, 12)
-
-
13. An image array pixel comprising:
-
a change storing node;
a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node; and
a source-follower transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions of said source-follower transistor being coupled to said first and second voltage and to said one of said source/drain regions of said reset transistor. - View Dependent Claims (14, 15, 16, 17)
-
-
18. An image array comprising:
-
a pixel cell;
a power supply circuit for selectively providing a first and second reset voltage; and
a switch circuit for coupling said power supply circuit to a storage node of said pixel cell. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
33. A method of operating pixel of pixel array, said method comprising:
-
flooding a pixel in said array to clear any stored signal;
applying a first reset voltage to said charge storage area of said pixel;
sampling a first voltage signal from said charge storage area;
applying a second reset voltage to said charge storage area;
sampling a second voltage signal from said charge storage area; and
determining a difference between said first and second sampled voltage signals. - View Dependent Claims (34, 35, 36, 37, 38)
-
-
39. A method of determining the intermediate reset voltage of an image array, said method comprising:
-
sampling and storing a first set of integrated signals from an array of pixels;
applying a first reset voltage to said array of pixels;
sampling and storing a first set of reset signals from said array of pixels;
applying a second reset voltage to said array of pixels;
sampling and storing a second set of integrated signals from said array of pixels;
applying said first reset voltage to said array of pixels;
sampling and storing a second set of reset signals from said array of pixels; and
determining a difference between said first set and second set of sampled voltage signals. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
-
-
52. A processing system, comprising:
-
a processor;
an imager array coupled to said processor, one pixel of said image array comprising;
a charge sharing node; and
a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node. - View Dependent Claims (53, 54, 55)
-
-
56. A processor system, comprising:
-
a processor;
an imager array coupled to said processor, one pixel of said imager array comprising;
a pixel cell;
a power supply circuit for reflectively providing a first and second reset voltage; and
a switch circuit for coupling said power supply circuit to a storage node of said pixel cell. - View Dependent Claims (57, 58, 59, 60, 61, 62, 63, 64, 65, 66)
-
-
67. An imaging device, comprising:
-
a processor;
an imager array coupled to said processor, one pixel of said image array comprising;
a charge sharing node; and
a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to a first and second voltage, the other of said source/drain regions being coupled to said node. - View Dependent Claims (68, 69, 70)
-
Specification