In situ determination of resistivity, mobility and dopant concentration profiles

• US 20050052191A1
• Filed: 08/26/2004
• Published: 03/10/2005
• Est. Priority Date: 08/27/2003
• Status: Active Grant

• Current Assignee: Active Layer Parametrics, Inc.
• Original Assignee: Simon A. Prussin
• Inventors: Prussin, Simon A.
• Granted Patent: US 7,078,919 B2
• Time in Patent Office: Days
• US Class Current: 324/719
• CPC Class Codes: G01N 27/041 of a solid body
• CPC Class Codes: G01R 31/2648 Characterising semiconductor materials testing of materials or semi-finished products G01R31/2831; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

The present invention provides techniques for an in-situ measurement of resistivity profiles and dopant concentration distributions in semiconductor structures, such as shallow junctions. A substrate with a resistor test structure having a conduction circuit may be placed at a measurement station, surface layers may be successively removed from the conduction circuit at the measurement station, a sheet resistance of the conduction circuit may be measured at the measurement station after the removal of each surface layer to generate a plurality of sheet resistance measurements, and the resistivity profile may be calculated from the plurality of sheet resistance measurements.

Claims

1. A method of determining the resistivity profile in a pn structure or in the silicon surface layer on a SOI (silicon on insulator) structure comprising the steps of:

placing a substrate with a resistor test structure having a conduction circuit on said pn or SOI structure at a measurement station;

successively removing surface layers from the conduction circuit at the measurement station;

measuring a sheet resistance of the conduction circuit at the measurement station after the removal of each surface layer to generate a plurality of sheet resistance measurements;

and calculating the resistivity profile from the plurality of sheet resistance measurements.

2. The method of claim 1, further comprising measuring an initial sheet resistance of the conduction circuit prior to removal of any surface layers.

3. The method of claim 1, wherein the removal of the layers from the conductive circuit is accomplished by repeated or continued anodic oxidation of the surface.

4. The method of claim 3, wherein anodic direct current is applied between a cathode and the test structure with a constant current source, and an incremental forming voltage is measured and used to determine a thickness of a removed surface layer.

5. The method of claim 3, wherein the anodic oxidation is carried out on a small area where the test structure is located.

6. The method of claim 3, wherein the resistor test structure is a cross van der Pauw resistor, and wherein the anodic oxidation is confined to the intersection of the arms of the cross van der Pauw resistor.

7. The method of claim 3, wherein measuring the sheet resistance measurement is performed without removing a surface oxide or an overlying electrolyte.

8. The method of claim 1, further comprising calculating a dopant concentration distribution of the pn structure or silicon surface layer from the resistivity profile.

9. The method of claim 8, wherein the dopant concentration distribution is calculated from the resistivity profile on the basis of specific mobility data.

10. The method of claim 8, wherein the dopant concentration distribution is calculated from the resistivity profile on the basis of A.S.T.M. Standard F723.

11. The method of claim 1, wherein the resistor test structure is a cross van der Pauw resistor.

12. The method of claim 11, wherein the resistance is measured by applying an alternating current through two arms of the van der Pauw resistor and measuring the voltage drop across the contacts on the opposite two arms.

13. The method of claim 1, wherein removing surface layers from the conduction circuit is carried out non-destructively on a production wafer such that the production wafer can be returned to the production process.

14. The method of claim 1, further comprising applying a magnetic field to the resistor test structure and measuring Hall sheet coefficients.

15. The method of claim 14, further comprising calculating a mobility profile from the Hall sheet coefficients.

16. A method of characterizing a semiconductor layer, comprising:

processing a production integrated circuit substrate to form a test structure having an electrically isolated semiconductor layer at a substrate surface;

receiving the substrate at a measurement station;

successively excluding a plurality of semiconductor sublayers from the surface of the semiconductor layer;

making a respective sheet resistance measurement of the semiconductor layer after the exclusion of each of the plurality of sublayers to provide a plurality of resistance measurements;

calculating a resistivity profile for the semiconductor layer from the plurality of resistance measurements; and

after making the plurality of resistance measurements, performing at least one additional processing step on the substrate in the fabrication of integrated circuits on the substrate.

17. A method of characterizing a semiconductor layer, comprising:

receiving at a measurement station a substrate that includes a structure having an electrically isolated semiconductor layer at a substrate surface;

while the substrate is at the measurement station successively excluding a plurality of semiconductor sublayers from the surface of the semiconductor layer;

making a respective sheet resistance measurement at the measurement station of the semiconductor layer after the exclusion of each of the plurality of sublayers to provide a plurality of resistance measurements; and

calculating a resistivity profile for the semiconductor layer from the plurality of resistance measurements.

18. A method of characterizing a semiconductor layer, comprising:

receiving at a measurement station a substrate that includes a structure having an electrically isolated semiconductor layer at a substrate surface;

successively oxidizing a plurality of semiconductor sublayers from the surface of the semiconductor layer to provide an oxidized portion on the surface of the substrate;

making a respective sheet resistance measurement of the semiconductor layer after the exclusion of each of the plurality of sublayers and while the oxidized portion is on the surface of the substrate to provide a plurality of resistance measurements; and

calculating a resistivity profile for the semiconductor layer from the plurality of resistance measurements.

19. A method of characterizing a semiconductor layer, comprising:

receiving at a measurement station a substrate that includes a structure having an electrically isolated semiconductor layer that provides a van der Pauw resistor having a central portion and four arms extending from the central portion at a substrate surface;

successively excluding a plurality of semiconductor sublayers in the central portion of the van der Pauw resistor;

making a respective sheet resistance measurement of the semiconductor layer after the exclusion of each of the plurality of sublayers by making electrical contact to arms of the van der Pauw resistor to provide a plurality of resistance measurements; and

calculating a resistivity profile for the semiconductor layer from the plurality of resistance measurements.

20. A method for characterizing layers in semiconductor substrates, the method comprising:

using anodic oxidation to convert a layer of a semiconductor substrate into an anodic oxide layer in a test region defined on the surface of the substrate; and

measuring a sheet resistance in the test region including the anodic oxide layer.

21. The method of claim 20, wherein the semiconductor substrate includes a silicon substrate.

22. The method of claim 20, wherein converting the layer of the substrate into the anodic oxide layer in the test region includes:

positioning a receptacle over the test region, the receptacle defining an opening to the test region within a limited area;

adding an electrolyte into the receptacle positioned over the test region, the electrolyte contacting the test region in the limited are; and

applying an electric current through the electrolyte and the substrate.

23. The method of claim 22, wherein:

positioning the receptacle over the test region includes placing a seal between the substrate and the opening of the receptacle.

24. The method of claim 22, wherein the electrolyte includes an aqueous solution.

25. The method of claim 22, wherein the electrolyte includes a non-aqueous solution.

26. The method of claim 20, wherein:

measuring the sheet resistance includes measuring a sequence of values for the sheet resistance, each value measured for the sheet resistance at a different depth of the anodic oxide layer.

27. The method of claim 26, further comprising:

determining a respective depth of the anodic oxide layer for each value measured for the sheet resistance.

28. The method of claim 27, wherein:

converting the layer of the substrate into the anodic oxide layer includes applying a predetermined electric current between a cathode and the substrate; and

determining the depth of the anodic oxide layer includes determining the depth of the anodic oxide layer based on a voltage drop between the cathode and the substrate.

29. The method of claim 27, further comprising:

determining one or more values of a differential resistivity based on two or more of the values measured for the sheet resistance, each value of the differential resistivity being determined for a respective depth in the substrate.

30. The method of claim 29, further comprising:

estimating a dopant distribution in the substrate based on the determined values of the differential resistivity.

31. The method of claim 20, wherein:

measuring the sheet resistance includes measuring the sheet resistance while the layer of the substrate is converted into the oxide layer.

32. The method of claim 20, wherein:

measuring the sheet resistance includes suspending the conversion of the layer of the substrate into the oxide layer while the sheet resistance is measured.

33. The method of claim 22, wherein:

the test structure includes a van der Pauw resistor.

34. The method of claim 33, wherein the test structure includes a central portion and four elongated arms attached to the central portion, and wherein:

measuring the sheet resistance in the test region includes passing a test current through two adjacent arms of the test structure and measuring voltage across two of the remaining arms of the test structure.

35. The method of claim 34, wherein the test current includes an alternating current.

36. The method of claim 20, further comprising applying a magnetic field to the test region and measuring a Hall sheet coefficient.

37. The method of claim 36, further comprising applying a positive magnetic field to the test region and measuring a first Hall sheet coefficient and applying a negative magnetic field to the test region and measuring a second Hall sheet coefficient.

38. The method of claim 36, wherein:

measuring the Hall sheet coefficient includes measuring a sequence of values for the Hall sheet coefficient, each value measured for the Hall sheet coefficient at a different depth of the anodic oxide layer.

39. A system for characterizing layers in semiconductor substrates, the system comprising:

a receptacle configured to receive an electrolyte and confine the received electrolyte to contact a surface of a semiconductor substrate in a limited test region;

a cathode configured to make electrical contact with the electrolyte in the receptacle;

an anodic current generator configured to pass an electric current through the cathode and the electrolyte to the substrate to convert a layer of the substrate into an anodic oxide layer in the test region; and

a sheet resistance meter configured to measure sheet resistance in the test region including the anodic oxide layer.

40. The system of claim 39, further comprising:

a controller to control the anodic current generator or the sheet resistance meter.

41. The system of claim 39, further comprising:

a first voltage meter configured to measure a voltage drop between the cathode and the substrate.

42. The system of claim 39, wherein the sheet resistance meter is configured to make electric contacts with four contact points arranged around a singly connected region of a test structure in the test region.

43. The system of claim 42, wherein the sheet resistance meter includes:

a test current generator to pass a test current through two adjacent contact points of the test structure; and

a second voltage meter to measure voltage across two of the remaining contact points of the test structure.

44. The system of claim 43, further comprising a magnet to apply a magnetic field to the test region.

45. The system of claim 44, wherein the sheet resistance meter is configured to measure a Hall sheet coefficient.