Method and apparatus for efficient preamble detection in digital data receivers

• US 20050063493A1
• Filed: 09/16/2004
• Published: 03/24/2005
• Est. Priority Date: 09/18/2003
• Status: Active Grant

• Current Assignee: Promptu Systems Corporation
• Original Assignee: Mark J. Foster
• Inventors: Foster, Mark J.
• Granted Patent: US 7,428,273 B2
• Time in Patent Office: Days
• US Class Current: 375/329
• CPC Class Codes: H04L 27/227 using coherent demodulation

Abstract

Traditional techniques for data reception in burst-mode receivers are of significant complexity. To aid detection, most burst-mode systems transmit a preamble, or predetermined data pattern, at the start of each new block of data. Using current methods, the detection of a new preamble, indicating the arrival of a new burst of data, is particularly complex. A method and apparatus is disclosed that significantly reduces this detection complexity, while maintaining superior signaling performance. This simplification can lead to higher data throughput within processing-limited receivers, and/or a greater degree of parallelism in multiple channel receivers.

Claims

1. A method for preamble detection in digital data receivers, comprising the steps of:

providing a power estimation means for producing a value of modulation power where;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N)).

2. The method of claim 1, said digital data comprising any of the following phase modulation formats:

QPSK, MPSK, and QAM.

3. A preamble detector for OPSK, comprising:

an input for receiving digitized input I and Q samples, wherein said input I and Q samples represent a reconstructed base band form of QPSK modulation;

a carrier derotation means for aligning said incoming signal phases with I and Q axes;

sign means for producing a ‘

1’

if said I and Q samples are greater than or equal to 0, or a ‘

0’

if said samples are less than 0;

sample delay means for providing chains of N-sample delays to yield one symbol-length delay for both I and Q;

a differential decoder for combining a current symbol state with a prior symbol state to yield a differentially decoded symbol value;

a multiplexer for alternating between a least-significant and a most-significant bit of said differentially decoded symbol values; and

a preamble shift register containing a serial-sequential representation of a received data stream.

4. The detector of claim 3:

wherein said shift register length is twice a number of bits in a preamble; and

wherein binary data bits are clocked into said preamble shift register at two bits/sample.

5. The detector of claim 4, said shift register further comprising:

XOR means for locating a unique preamble data pattern in accordance with the following;

Preamble_Mismatch=Preamble-Register XOR PREAMBLE_PATTERN

wherein said PREAMBLE_PATTERN is a bit-pair doubled representation of a unique data pattern that defines an implementation-specific value for said preamble;

wherein Preamble_Mismatch indicates outputs of said XOR means;

wherein said XOR means invert any bits in said preamble that should be a binary ‘

1;

’ and

wherein when outputs of said XOR means all become zero, indicating no mismatch, a data pattern has been identified that matches a desired preamble data pattern.

6. The detector of claim 5, further comprising:

means for producing a value of modulation power, where;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N)).

7. The detector of claim 5, further comprising:

a comparator for comparing said signal power level to a predetermined minimum acceptable power threshold;

wherein an output of said comparator is a ‘

1’

if an input signal level is too low to be considered a valid transmission, and said comparator output is ‘

0’

if said power level exceeds said threshold;

a Power_Invalid shift register which receives said comparator output, said Power_Invalid shift register containing a history of an invalidity status of recent samples; and

OR means for merging Power_Invalid flags with Preamble_Mismatch outputs, resulting in a product expression of;

Preamble_Status=Preamble_Mismatch OR Power_Invalid

wherein a candidate preamble has both a proper bit polarity and a proper signal level; and

wherein said OR means combine said I and Q data bits, whereby if either of said I or Q samples have incorrect signs, then an output of that sample from said OR means becomes true to indicate a non-matching symbol.

8. The detector of claim 7, further comprising:

AND means for isolating N-1 out of N samples to ignore one sample/symbol during which zero-crossings may occur;

wherein with two samples/symbol, said AND means isolates alternate samples.

9. The detector of claim 8, further comprising:

NOR means;

wherein once all relevant samples have proper signs, and have been received with a sufficient power level, an output of said NOR means is driven high, indicating Preamble_Found;

wherein said detector begins the process of receiving a new data burst.

10. The detector of claim 3, wherein, if a preamble used is an unchanging constant, said detector further comprising:

NOT means inserted selectively at any sample timing offset where an expected value of a preamble is ‘

1.’

11. The detector of claim 3, wherein said shift register is extendable to use said detector with any integer number of samples/symbol, or any preamble length.

12. A differential preamble detector for QPSK, comprising:

an input for receiving digitized input I and Q samples;

delay means for yielding one-symbol delayed versions of both signals;

at least one multiplier for computing partial products of said I and Q samples and a complex conjugate of a delayed signal, yielding phase component real(Z_k), without computing imag(Z_k), with regard to a differential phase function;

real(Z_k)=real(R_k)·

real(R_k-N)+imag(R_k)·

imag(R_k-N);

an adder for summing said phase components to yield a differential phase sample real(Z_k);

sign means for producing a differential phase bit that flags 0-degree relative phase shifts with a ‘

1,’ and

180-degree samples with a ‘

0;

’

said phase bits being sequentially clocked into a preamble shift register in the form of a serially-concatenated phase sequence; and

exclusive OR means for exclusive-ORing a nominal preamble phase sequence with a receive phase sequence.

13. The detector of claim 12, wherein a preamble phase sequence is inverted.

14. The detector of claim 12, further comprising:

power estimation means.

15. The detector of claim 14, said power estimation means comprising:

an absolute value operator for forcing said phase components to be positive; and

an adder summing said positive phase components to create a received signal power estimate.

16. The detector of claim 15, further comprising:

a comparator comparing said power estimate with a minimum power level necessary for a sample to be considered a valid received signal.

17. The detector of claim 16, further comprising:

an invalid power shift register into which a sequence of power invalidity states, corresponding to one bit per received sample, is clocked;

OR means, wherein when a signal sequence has been received which contains a minimum necessary power, and with correct sample phases, all outputs of said OR means are low; and

NOR means for detecting when all OR means outputs are low, and for outputting a high level at a preamble detection output, thereby flagging presence of a new data burst.

18. The detector of claim 14, wherein said power estimation means replaces conventional signal power measurement.

19. The detector of claim 18, wherein said modulation power value is used for any of preamble threshold detection, absolute signal strength, and received signal/noise ratio.

20. The detector of claim 12, further comprising:

a binary mask for removing samples that perform zero-crossings.

21. In a QPSK transmission system, a preamble detector comprising:

means for reducing all four QPSK states to a 1-bit representation which differentiates between two antipodal states.

22. The detector of claim 21, further comprising:

power threshold detection means for ensuring that non-antipodal signal transitions are not identified as valid antipodal preamble transitions.

23. A preamble detector, comprising:

power threshold detection means for ensuring that non-antipodal signal transitions are not identified as valid antipodal preamble transitions.

24. A power estimator, comprising:

an absolute value operator for forcing positive real and imaginary phase components of real(Z_k) with regard to a modulation power function;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N))

and

an adder summing said positive phase components to create a received signal power estimate.

25. The power estimator of claim 24, further comprising:

a comparator comparing said power estimate with a minimum power level necessary for a sample to be considered a valid received signal.

26. The power estimator of claim 25, further comprising:

an invalid power shift register into which a sequence of power invalidity states, corresponding to one bit per received sample, is clocked;

OR means, wherein when a signal sequence has been received which contains a minimum necessary power, and with correct sample phases, all outputs of said OR means are low; and

NOR means for detecting when all OR means outputs are low, and for outputting a high level at a preamble detection output, thereby flagging presence of a new data burst.

27. An apparatus for preamble detection in digital data receivers, comprising:

power estimation means for producing a value of modulation power, wherein;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N)).

28. The apparatus of claim 27, said digital data comprising any of the following modulation formats:

QPSK, MPSK, and QAM.

29. A preamble detection method for QPSK, comprising the steps of:

receiving digitized input I and Q samples, wherein said input I and Q samples represent a reconstructed base band form of QPSK modulation;

aligning said incoming signal phases with I and Q axes;

producing a ‘

1’

if said I and Q samples are greater than or equal to 0, or a ‘

0’

if said samples are less than 0;

providing chains of N-sample delays to yield one symbol-length delay for both I and Q;

combining a current symbol state with a prior symbol state to yield a differentially decoded symbol value;

alternating between a least-significant and a most-significant bit of said differentially decoded symbol values; and

providing a serial-sequential representation of a received data stream.

30. The detection method of claim 29:

wherein said serial-sequential representation of a received data stream length is twice a number of bits in a preamble; and

wherein binary data bits are clocked in at two bits/sample.

31. The detection method of claim 30, further comprising the step of:

locating a unique preamble data pattern in accordance with the following;

Preamble_Mismatch=Preamble_Register XOR PREAMBLE_PATTERN

wherein said PREAMBLE_PATTERN is a bit-pair doubled representation of a unique data pattern that defines an implementation-specific value for said preamble;

wherein Preamble_Mismatch indicates an XOR output;

wherein any bits in said preamble that should be a binary ‘

1’

are inverted; and

wherein when said XOR output becomes zero, indicating no mismatch, a data pattern has been identified that matches a desired preamble data pattern.

32. The detection method of claim 31, further comprising the step of:

implementing a power estimation function;

producing a value of modulation power, where;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N)).

33. The detection method of claim 31, further comprising the steps of:

comparing said signal power level to a predetermined minimum acceptable power threshold;

wherein an output of said comparing step is a ‘

1’

if an input signal level is too low to be considered a valid transmission, and said comparing step output is ‘

0’

if said power level exceeds said threshold;

receiving said comparing step output a Power_Invalid shift register, said Power_Invalid shift register containing a history of an invalidity status of recent samples; and

merging Power_Invalid flags with Preamble_Mismatch outputs, resulting in a product expression of;

Preamble_Status=Preamble_Mismatch OR Power_Invalid

wherein a candidate preamble has both a proper bit polarity and a proper signal level; and

wherein said merging step combines said I and Q data bits, whereby if either of said I or Q samples have incorrect signs, then an output of that sample from said merging step becomes true to indicate a non-matching symbol.

34. The detection method of claim 33, further comprising the step of:

isolating N-1 out of N samples to ignore one sample/symbol during which zero-crossings may occur;

wherein with two samples/symbol, alternate samples are isolated.

35. The detection method of claim 34, wherein once all relevant samples have proper signs, and have been received with a sufficient power level, an output is driven high, indicating Preamble_Found;

wherein said detector begins the process of receiving a new data burst.

36. The detection method of claim 29, wherein, if a preamble used is an unchanging constant, said detector further comprising the step of:

inserting a NOT function selectively at any sample timing offset where an expected value of a preamble is ‘

1.’

37. The detection method of claim 29, further comprising the step of:

extending said detector with any integer number of samples/symbol, or any preamble length.

38. A differential preamble detection method for QPSK, comprising the steps of:

receiving digitized input I and Q samples;

providing one-symbol delayed versions of both signals;

computing partial products of said I and Q samples and a complex conjugate of a delayed signal, yielding phase components of real(Z_k), without computing imag(Z_k), with regard to a differential phase function;

real(Z_k)=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N)).

summing said phase components to yield a differential phase sample real(Z_k);

producing a differential phase bit that flags 0-degree relative phase shifts with a ‘

1,’ and

180-degree samples with a ‘

0;

’

sequentially clocking said phase bits into a preamble shift register in the form of a serially-concatenated phase sequence; and

exclusive-ORing a nominal preamble phase sequence with a receive phase sequence.

39. The detection method of claim 38, wherein a preamble phase sequence is inverted.

40. The detection method of claim 38, further comprising the step of:

performing power estimation.

41. The detection method of claim 40, said power estimation step comprising the steps of:

forcing said phase components to be positive with an absolute value operator; and

summing said positive phase components to create a received signal power estimate.

42. The detection method of claim 41, further comprising the step of:

comparing said power estimate with a minimum power level necessary for a sample to be considered a valid received signal.

43. The detection method of claim 42, further comprising the steps of:

clocking a sequence of power invalidity states, corresponding to one bit per received sample, into an invalid power shift register;

wherein when a signal sequence has been received which contains a minimum necessary power, and with correct sample phases, all outputs of an OR gate are low;

detecting when all OR gate outputs are low; and

outputting a high level at a preamble detection output, thereby flagging presence of a new data burst.

44. The detection method of claim 41, wherein said power estimation step replaces conventional signal power measurement.

45. The detection method of claim 44, wherein said modulation power value is used for any of preamble threshold detection, absolute signal strength, and received signal/noise ratio.

46. The detection method of claim 38, further comprising the step of:

removing samples that perform zero-crossings with a binary mask.

47. In a QPSK transmission system, a preamble detection method comprising the step of:

reducing all four QPSK states to a 1-bit representation which differentiates between two antipodal states.

48. The detection method of claim 47, further comprising the step of:

providing power threshold detection means for ensuring that non-antipodal signal transitions are not identified as valid antipodal preamble transitions.

49. A preamble detection method, comprising the step of:

providing power threshold detection means for ensuring that non-antipodal signal transitions are not identified as valid antipodal preamble transitions.

50. A power estimation method, comprising the steps of:

using an absolute value operator for forcing positive real and imaginary phase components of real(Z_k) with regard to a modulation power function;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N))

and

summing said positive phase components to create a received signal power estimate.

51. The power estimation method of claim 50, further comprising the step of:

comparing said power estimate with a minimum power level necessary for a sample to be considered a valid received signal.

52. The power estimation method of claim 51, further comprising the steps of:

providing an invalid power shift register into which a sequence of power invalidity states, corresponding to one bit per received sample, is clocked;

providing OR means, wherein when a signal sequence has been received which contains a minimum necessary power, and with correct sample phases, all outputs of said OR means are low; and

detecting when all OR means outputs are low, and for outputting a high level at a preamble detection output, thereby flagging presence of a new data burst.