Intra-chip power and test signal generation for use with test structures on wafers
First Claim
1. An arrangement for evaluating a fabrication of at least a partially-fabricated wafer, wherein the arrangement comprises:
- a circuit element provided within an active region of a die of the wafer;
a power receiver provided in the active region of the die and connected to the circuit element, wherein the power receiver is configured to generate a power signal for the circuit element in response to receiving a power input;
a test/trigger receiver provided in the active region of the die and connected to the circuit element, wherein the test/trigger receiver is configured to generate a trigger signal for the circuit element in response to receiving a signal input;
wherein in response to receiving the power signal and the trigger signal, the circuit element is configured to exhibit an electrical activity that is detectable by a test probe without affecting a usability of a chip that is formed from the die, and wherein the electrical activity is indicative of one or more characteristics that are a result of the fabrication.
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0 Petitions
Accused Products
Abstract
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
135 Citations
44 Claims
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1. An arrangement for evaluating a fabrication of at least a partially-fabricated wafer, wherein the arrangement comprises:
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a circuit element provided within an active region of a die of the wafer;
a power receiver provided in the active region of the die and connected to the circuit element, wherein the power receiver is configured to generate a power signal for the circuit element in response to receiving a power input;
a test/trigger receiver provided in the active region of the die and connected to the circuit element, wherein the test/trigger receiver is configured to generate a trigger signal for the circuit element in response to receiving a signal input;
wherein in response to receiving the power signal and the trigger signal, the circuit element is configured to exhibit an electrical activity that is detectable by a test probe without affecting a usability of a chip that is formed from the die, and wherein the electrical activity is indicative of one or more characteristics that are a result of the fabrication. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor wafer comprising:
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a die having an active region on which one or more devices are provided;
a test structure positioned in the active region;
a power receiver provided in the active region and connected to the test structure, wherein the power receiver is configured to generate a power signal for the test structure in response to receiving a power input;
a test/trigger receiver positioned in the active region and coupled to the test structure, wherein the test/trigger receiver is configured to generate a trigger signal for the test structure in response to receiving a signal input;
wherein in response to receiving the power signal and the trigger signal, the test structure is configured to exhibit an electrical activity that is detectable by a test probe without affecting a usability of integrated circuit elements provided on the die, and wherein the electrical activity is indicative of one or more characteristics that are a result of a fabrication of the wafer. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for evaluating a fabrication of a semiconductor wafer, the method comprising the steps of:
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causing power to be generated from within the die and to be supplied to the test structure;
causing a trigger signal to be generated from within a die of the wafer and to be supplied to a test structure;
detecting electrical activity exhibited by the test structure upon the trigger signal and power being supplied to the test structure;
correlating the detected electrical activity to a step or sequence of the fabrication of the wafer. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33)
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34. A method for measuring electrical characteristics of a die on at least a partially fabricated semiconductor wafer, said method comprising:
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generating a power signal from within the die by energizing a first set of one or more predetermined areas inside the die using either the first external energy source;
generating a trigger signal from within the die by energizing a second set of one or more predetermined areas inside the die using a first external energy source or a second external energy source, wherein the predetermined areas are stimulated without mechanical contact between the external energy source and the die;
detecting an electrical activity within the die as a result of the trigger signal being generated; and
determining a characteristics of at least a component in the die based on the detected electrical activity. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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Specification